OpenFPGA/docs/source/fpga_spice/customize_subckt.rst

Create Customized SPICE Modules
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To make sure the customized SPICE netlists can be correctly included in FPGA-SPICE, the following rules should be fully respected:

1.    The customized SPICE netlists could contain multiple sub-circuits but the names of these sub-circuits should not be conflicted with any reserved words.. Here is an example of defining a sub-circuit in SPICE netlists. The <subckt_name> should be a unique one, which should not be conflicted with any reserved words.
.subckt <subckt_name> <ports> 

2.    The ports of sub-circuit to be included should strictly follow the sequence:
<input_ports> <output_ports> <sram_ports> <clock_ports> <vdd> <gnd>
It is not necessary to keep the names of ports be the same with what is defined in the SPICE models. But the bandwidth of the ports should be consistent with what is defined in the Circuit models.

.. note:: If the customized SPICE netlists include inverters, buffers or transmission gates, it is recommended to use those auto-generated by FPGA-SPICE. It is also recommended to use the transistor sub-circuit (vpr_nmos and vpr_pmos) auto-generated by FPGA-SPICE. In the appendix, we introduce how to use these useful sub-circuits.
Update a draft 2018-09-13 23:58:54 -05:00			`Create Customized SPICE Modules`
			`===============================`
			`To make sure the customized SPICE netlists can be correctly included in FPGA-SPICE, the following rules should be fully respected:`
Documentation_code&example_update 2018-10-12 16:50:09 -05:00
Update customize_subckt.rst 2019-04-01 17:27:06 -05:00			`1. The customized SPICE netlists could contain multiple sub-circuits but the names of these sub-circuits should not be conflicted with any reserved words.. Here is an example of defining a sub-circuit in SPICE netlists. The <subckt_name> should be a unique one, which should not be conflicted with any reserved words.`
Update a draft 2018-09-13 23:58:54 -05:00			`.subckt <subckt_name> <ports>`

Update customize_subckt.rst 2019-04-01 17:27:06 -05:00			`2. The ports of sub-circuit to be included should strictly follow the sequence:`
Update a draft 2018-09-13 23:58:54 -05:00			`<input_ports> <output_ports> <sram_ports> <clock_ports> <vdd> <gnd>`
Documentation_code&example_update 2018-10-12 16:50:09 -05:00			`It is not necessary to keep the names of ports be the same with what is defined in the SPICE models. But the bandwidth of the ports should be consistent with what is defined in the Circuit models.`
Update a draft 2018-09-13 23:58:54 -05:00
Update customize_subckt.rst 2019-04-01 17:27:06 -05:00			`.. note:: If the customized SPICE netlists include inverters, buffers or transmission gates, it is recommended to use those auto-generated by FPGA-SPICE. It is also recommended to use the transistor sub-circuit (vpr_nmos and vpr_pmos) auto-generated by FPGA-SPICE. In the appendix, we introduce how to use these useful sub-circuits.`
Update a draft 2018-09-13 23:58:54 -05:00