21 lines
470 B
Tcl
21 lines
470 B
Tcl
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# = = = = = = = = = = = = = = = = = = = = = =
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# Auto generated using OpenFPGA
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# = = = = = = = = = = = = = = = = = = = = = =
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# Benchmark Source Files
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read_verilog -container r -libname WORK -05 { ${SOURCE_DESIGN_FILES} }
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set_top r:${SOURCE_TOP_MODULE}
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# Benchmark Implementation Files
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read_verilog -container i -libname WORK -05 { ${IMPL_DESIGN_FILES} }
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set_top i:${IMPL_TOP_DIR}
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match
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# Port Mapping
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${PORT_MAP_LIST}
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# Register Mapping
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${REGISTER_MAP_LIST}
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verify
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