1055 lines
35 KiB
Coq
1055 lines
35 KiB
Coq
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// originally created by Marcus van Ierssel
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// modified by Ahmad Darabiha, Feb. 2002
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// this circuit receives the rgbvideo signal
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// from video input and send it to chip #2
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// for buffring and processing.
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module sv_chip3_hierarchy_no_mem (tm3_clk_v0, tm3_clk_v2, tm3_vidin_llc, tm3_vidin_vs, tm3_vidin_href, tm3_vidin_cref, tm3_vidin_rts0, tm3_vidin_vpo, tm3_vidin_sda, tm3_vidin_scl, vidin_new_data, vidin_rgb_reg, vidin_addr_reg);
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input tm3_clk_v0;
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input tm3_clk_v2;
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input tm3_vidin_llc;
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input tm3_vidin_vs;
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input tm3_vidin_href;
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input tm3_vidin_cref;
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input tm3_vidin_rts0;
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input[15:0] tm3_vidin_vpo;
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output tm3_vidin_sda;
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wire tm3_vidin_sda;
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reg tm3_vidin_sda_xhdl0;
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output tm3_vidin_scl;
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reg tm3_vidin_scl;
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output vidin_new_data;
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reg vidin_new_data;
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output[7:0] vidin_rgb_reg;
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reg[7:0] vidin_rgb_reg;
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output[18:0] vidin_addr_reg;
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reg[18:0] vidin_addr_reg;
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reg temp_reg1;
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reg temp_reg2;
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reg[9:0] horiz;
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reg[7:0] vert;
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reg creg1;
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reg creg2;
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reg creg3;
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reg[18:0] vidin_addr_reg1;
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reg[23:0] vidin_rgb_reg1;
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reg[23:0] vidin_rgb_reg2;
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parameter[4:0] reg_prog1 = 5'b00001;
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parameter[4:0] reg_prog2 = 5'b00010;
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parameter[4:0] reg_prog3 = 5'b00011;
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parameter[4:0] reg_prog4 = 5'b00100;
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parameter[4:0] reg_prog5 = 5'b00101;
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parameter[4:0] reg_prog6 = 5'b00110;
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parameter[4:0] reg_prog7 = 5'b00111;
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parameter[4:0] reg_prog8 = 5'b01000;
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parameter[4:0] reg_prog9 = 5'b01001;
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parameter[4:0] reg_prog10 = 5'b01010;
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parameter[4:0] reg_prog11 = 5'b01011;
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parameter[4:0] reg_prog12 = 5'b01100;
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parameter[4:0] reg_prog13 = 5'b01101;
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parameter[4:0] reg_prog14 = 5'b01110;
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parameter[4:0] reg_prog15 = 5'b01111;
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parameter[4:0] reg_prog16 = 5'b10000;
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parameter[4:0] reg_prog17 = 5'b10001;
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parameter[4:0] reg_prog18 = 5'b10010;
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parameter[4:0] reg_prog19 = 5'b10011;
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parameter[4:0] reg_prog20 = 5'b10100;
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parameter[4:0] reg_prog21 = 5'b10101;
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parameter[4:0] reg_prog22 = 5'b10110;
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parameter[4:0] reg_prog23 = 5'b10111;
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parameter[4:0] reg_prog24 = 5'b11000;
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parameter[4:0] reg_prog25 = 5'b11001;
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parameter[4:0] reg_prog26 = 5'b11010;
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parameter[4:0] reg_prog_end = 5'b11011;
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reg rst;
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reg rst_done;
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reg[7:0] iicaddr;
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reg[7:0] iicdata;
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// wire vidin_llc;
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// wire vidin_llc_int;
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reg[6:0] iic_state;
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reg iic_stop;
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reg iic_start;
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reg[4:0] reg_prog_state;
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reg[4:0] reg_prog_nextstate;
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assign tm3_vidin_sda = tm3_vidin_sda_xhdl0;
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// ibuf ibuf_inst (tm3_vidin_llc, vidin_llc_int);
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// bufg bufg_inst (vidin_llc_int, vidin_llc);
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// PAJ double clock is trouble...always @(vidin_llc)
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always @(posedge tm3_clk_v0)
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begin
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if (tm3_vidin_href == 1'b0)
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begin
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horiz <= 10'b0000000000 ;
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end
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else
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begin
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if (tm3_vidin_cref == 1'b0)
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begin
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horiz <= horiz + 1 ;
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end
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end
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if (tm3_vidin_vs == 1'b1)
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begin
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vert <= 8'b00000000 ;
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end
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else
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begin
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if ((tm3_vidin_href == 1'b0) & (horiz != 10'b0000000000))
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begin
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vert <= vert + 1 ;
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end
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end
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if (tm3_vidin_cref == 1'b1)
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begin
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vidin_rgb_reg1[23:19] <= tm3_vidin_vpo[15:11] ;
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vidin_rgb_reg1[15:13] <= tm3_vidin_vpo[10:8] ;
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vidin_rgb_reg1[18:16] <= tm3_vidin_vpo[7:5] ;
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vidin_rgb_reg1[9:8] <= tm3_vidin_vpo[4:3] ;
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vidin_rgb_reg1[2:0] <= tm3_vidin_vpo[2:0] ;
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vidin_rgb_reg2 <= vidin_rgb_reg1 ;
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end
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else
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begin
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vidin_rgb_reg1[12:10] <= tm3_vidin_vpo[7:5] ;
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vidin_rgb_reg1[7:3] <= tm3_vidin_vpo[4:0] ;
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vidin_addr_reg1 <= {vert, tm3_vidin_rts0, horiz} ;
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end
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end
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always @(posedge tm3_clk_v0)
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begin
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creg1 <= tm3_vidin_cref ;
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creg2 <= creg1 ;
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creg3 <= creg2 ;
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if ((creg2 == 1'b0) & (creg3 == 1'b1) & ((vidin_addr_reg1[10]) == 1'b0) & ((vidin_addr_reg1[0]) == 1'b0))
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begin
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vidin_new_data <= 1'b1 ;
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vidin_rgb_reg <= vidin_rgb_reg2[7:0] ;
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vidin_addr_reg <= {({2'b00, vidin_addr_reg1[18:11]}), vidin_addr_reg1[9:1]} ;
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end
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else
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begin
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vidin_new_data <= 1'b0 ;
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end
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end
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always @(posedge tm3_clk_v2)
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begin
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// A: Worked around scope issue by moving iic_stop into every case.
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case (iic_state)
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7'b0000000 :
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begin
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iic_stop <= 1'b0 ;
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tm3_vidin_sda_xhdl0 <= 1'b0 ;
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tm3_vidin_scl <= 1'b1 ;
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end
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7'b0000001 :
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begin
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iic_stop <= 1'b0 ;
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tm3_vidin_sda_xhdl0 <= 1'b1 ;
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tm3_vidin_scl <= 1'b1 ;
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end
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7'b0000010 :
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begin
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iic_stop <= 1'b0 ;
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tm3_vidin_sda_xhdl0 <= 1'b0 ;
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tm3_vidin_scl <= 1'b1 ;
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end
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7'b0000011 :
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begin
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iic_stop <= 1'b0 ;
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tm3_vidin_sda_xhdl0 <= 1'b0 ;
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tm3_vidin_scl <= 1'b0 ;
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end
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7'b0000100 :
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begin
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iic_stop <= 1'b0 ;
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tm3_vidin_sda_xhdl0 <= 1'b0 ;
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tm3_vidin_scl <= 1'b1 ;
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end
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7'b0000101 :
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begin
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iic_stop <= 1'b0 ;
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tm3_vidin_sda_xhdl0 <= 1'b0 ;
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tm3_vidin_scl <= 1'b0 ;
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end
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7'b0000110 :
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begin
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iic_stop <= 1'b0 ;
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tm3_vidin_sda_xhdl0 <= 1'b1 ;
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tm3_vidin_scl <= 1'b0 ;
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end
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7'b0000111 :
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begin
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iic_stop <= 1'b0 ;
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tm3_vidin_sda_xhdl0 <= 1'b1 ;
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tm3_vidin_scl <= 1'b1 ;
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end
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7'b0001000 :
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begin
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iic_stop <= 1'b0 ;
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tm3_vidin_sda_xhdl0 <= 1'b1 ;
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tm3_vidin_scl <= 1'b0 ;
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end
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7'b0001001 :
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begin
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iic_stop <= 1'b0 ;
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tm3_vidin_sda_xhdl0 <= 1'b0 ;
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tm3_vidin_scl <= 1'b0 ;
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end
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7'b0001010 :
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begin
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iic_stop <= 1'b0 ;
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tm3_vidin_sda_xhdl0 <= 1'b0 ;
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tm3_vidin_scl <= 1'b1 ;
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end
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7'b0001011 :
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begin
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iic_stop <= 1'b0 ;
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tm3_vidin_sda_xhdl0 <= 1'b0 ;
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tm3_vidin_scl <= 1'b0 ;
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end
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7'b0001100 :
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begin
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iic_stop <= 1'b0 ;
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tm3_vidin_sda_xhdl0 <= 1'b0 ;
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tm3_vidin_scl <= 1'b1 ;
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end
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7'b0001101 :
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begin
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iic_stop <= 1'b0 ;
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tm3_vidin_sda_xhdl0 <= 1'b0 ;
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tm3_vidin_scl <= 1'b0 ;
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end
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7'b0001110 :
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begin
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iic_stop <= 1'b0 ;
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tm3_vidin_sda_xhdl0 <= 1'b1 ;
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tm3_vidin_scl <= 1'b0 ;
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end
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7'b0001111 :
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begin
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iic_stop <= 1'b0 ;
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tm3_vidin_sda_xhdl0 <= 1'b1 ;
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tm3_vidin_scl <= 1'b1 ;
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end
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7'b0010000 :
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begin
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iic_stop <= 1'b0 ;
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tm3_vidin_sda_xhdl0 <= 1'b1 ;
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tm3_vidin_scl <= 1'b0 ;
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end
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7'b0010001 :
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begin
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iic_stop <= 1'b0 ;
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tm3_vidin_sda_xhdl0 <= 1'b0 ;
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tm3_vidin_scl <= 1'b0 ;
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end
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7'b0010010 :
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begin
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iic_stop <= 1'b0 ;
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tm3_vidin_sda_xhdl0 <= 1'b0 ;
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tm3_vidin_scl <= 1'b1 ;
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end
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7'b0010011 :
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begin
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iic_stop <= 1'b0 ;
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tm3_vidin_sda_xhdl0 <= 1'b0 ;
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tm3_vidin_scl <= 1'b0 ;
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end
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7'b0010101 :
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begin
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iic_stop <= 1'b0 ;
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tm3_vidin_sda_xhdl0 <= 1'b0 ;
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tm3_vidin_scl <= 1'b0 ;
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end
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7'b0010110 :
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begin
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iic_stop <= 1'b0 ;
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tm3_vidin_sda_xhdl0 <= 1'b0 ;
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tm3_vidin_scl <= 1'b1 ;
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end
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7'b0010111 :
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begin
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iic_stop <= 1'b0 ;
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tm3_vidin_sda_xhdl0 <= 1'b0 ;
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tm3_vidin_scl <= 1'b0 ;
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end
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7'b0011000 :
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begin
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iic_stop <= 1'b0 ;
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tm3_vidin_sda_xhdl0 <= 1'b0 ;
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tm3_vidin_scl <= 1'b1 ;
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end
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7'b0011001 :
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begin
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iic_stop <= 1'b0 ;
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tm3_vidin_sda_xhdl0 <= 1'b0 ;
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tm3_vidin_scl <= 1'b0 ;
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end
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7'b0011010 :
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begin
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iic_stop <= 1'b0 ;
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tm3_vidin_sda_xhdl0 <= iicaddr[7] ;
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tm3_vidin_scl <= 1'b0 ;
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end
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7'b0011011 :
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begin
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iic_stop <= 1'b0 ;
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tm3_vidin_sda_xhdl0 <= iicaddr[7] ;
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tm3_vidin_scl <= 1'b1 ;
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end
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7'b0011100 :
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begin
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iic_stop <= 1'b0 ;
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tm3_vidin_sda_xhdl0 <= iicaddr[7] ;
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tm3_vidin_scl <= 1'b0 ;
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end
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7'b0011101 :
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begin
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iic_stop <= 1'b0 ;
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tm3_vidin_sda_xhdl0 <= iicaddr[6] ;
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tm3_vidin_scl <= 1'b0 ;
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end
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7'b0011110 :
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begin
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iic_stop <= 1'b0 ;
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tm3_vidin_sda_xhdl0 <= iicaddr[6] ;
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tm3_vidin_scl <= 1'b1 ;
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end
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7'b0011111 :
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begin
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iic_stop <= 1'b0 ;
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tm3_vidin_sda_xhdl0 <= iicaddr[6] ;
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tm3_vidin_scl <= 1'b0 ;
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end
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7'b0100000 :
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begin
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iic_stop <= 1'b0 ;
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tm3_vidin_sda_xhdl0 <= iicaddr[5] ;
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tm3_vidin_scl <= 1'b0 ;
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end
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7'b0100001 :
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begin
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iic_stop <= 1'b0 ;
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|
|
tm3_vidin_sda_xhdl0 <= iicaddr[5] ;
|
||
|
|
tm3_vidin_scl <= 1'b1 ;
|
||
|
|
end
|
||
|
|
7'b0100010 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicaddr[5] ;
|
||
|
|
tm3_vidin_scl <= 1'b0 ;
|
||
|
|
end
|
||
|
|
7'b0100011 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicaddr[4] ;
|
||
|
|
tm3_vidin_scl <= 1'b0 ;
|
||
|
|
end
|
||
|
|
7'b0100100 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicaddr[4] ;
|
||
|
|
tm3_vidin_scl <= 1'b1 ;
|
||
|
|
end
|
||
|
|
7'b0100101 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicaddr[4] ;
|
||
|
|
tm3_vidin_scl <= 1'b0 ;
|
||
|
|
end
|
||
|
|
7'b0100110 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicaddr[3] ;
|
||
|
|
tm3_vidin_scl <= 1'b0 ;
|
||
|
|
end
|
||
|
|
7'b0100111 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicaddr[3] ;
|
||
|
|
tm3_vidin_scl <= 1'b1 ;
|
||
|
|
end
|
||
|
|
7'b0101000 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicaddr[3] ;
|
||
|
|
tm3_vidin_scl <= 1'b0 ;
|
||
|
|
end
|
||
|
|
7'b0101001 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicaddr[2] ;
|
||
|
|
tm3_vidin_scl <= 1'b0 ;
|
||
|
|
end
|
||
|
|
7'b0101010 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicaddr[2] ;
|
||
|
|
tm3_vidin_scl <= 1'b1 ;
|
||
|
|
end
|
||
|
|
7'b0101011 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicaddr[2] ;
|
||
|
|
tm3_vidin_scl <= 1'b0 ;
|
||
|
|
end
|
||
|
|
7'b0101100 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicaddr[1] ;
|
||
|
|
tm3_vidin_scl <= 1'b0 ;
|
||
|
|
end
|
||
|
|
7'b0101101 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicaddr[1] ;
|
||
|
|
tm3_vidin_scl <= 1'b1 ;
|
||
|
|
end
|
||
|
|
7'b0101110 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicaddr[1] ;
|
||
|
|
tm3_vidin_scl <= 1'b0 ;
|
||
|
|
end
|
||
|
|
7'b0101111 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicaddr[0] ;
|
||
|
|
tm3_vidin_scl <= 1'b0 ;
|
||
|
|
end
|
||
|
|
7'b0110000 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicaddr[0] ;
|
||
|
|
tm3_vidin_scl <= 1'b1 ;
|
||
|
|
end
|
||
|
|
7'b0110001 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicaddr[0] ;
|
||
|
|
tm3_vidin_scl <= 1'b0 ;
|
||
|
|
end
|
||
|
|
7'b0110010 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= 1'b0 ;
|
||
|
|
tm3_vidin_scl <= 1'b0 ;
|
||
|
|
end
|
||
|
|
7'b0110011 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= 1'b0 ;
|
||
|
|
tm3_vidin_scl <= 1'b1 ;
|
||
|
|
end
|
||
|
|
7'b0110100 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= 1'b0 ;
|
||
|
|
tm3_vidin_scl <= 1'b0 ;
|
||
|
|
end
|
||
|
|
7'b0110101 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicdata[7] ;
|
||
|
|
tm3_vidin_scl <= 1'b0 ;
|
||
|
|
end
|
||
|
|
7'b0110110 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicdata[7] ;
|
||
|
|
tm3_vidin_scl <= 1'b1 ;
|
||
|
|
end
|
||
|
|
7'b0110111 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicdata[7] ;
|
||
|
|
tm3_vidin_scl <= 1'b0 ;
|
||
|
|
end
|
||
|
|
7'b0111000 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicdata[6] ;
|
||
|
|
tm3_vidin_scl <= 1'b0 ;
|
||
|
|
end
|
||
|
|
7'b0111001 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicdata[6] ;
|
||
|
|
tm3_vidin_scl <= 1'b1 ;
|
||
|
|
end
|
||
|
|
7'b0111010 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicdata[6] ;
|
||
|
|
tm3_vidin_scl <= 1'b0 ;
|
||
|
|
end
|
||
|
|
7'b0111011 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicdata[5] ;
|
||
|
|
tm3_vidin_scl <= 1'b0 ;
|
||
|
|
end
|
||
|
|
7'b0111100 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicdata[5] ;
|
||
|
|
tm3_vidin_scl <= 1'b1 ;
|
||
|
|
end
|
||
|
|
7'b0111101 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicdata[5] ;
|
||
|
|
tm3_vidin_scl <= 1'b0 ;
|
||
|
|
end
|
||
|
|
7'b0111110 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicdata[4] ;
|
||
|
|
tm3_vidin_scl <= 1'b0 ;
|
||
|
|
end
|
||
|
|
7'b0111111 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicdata[4] ;
|
||
|
|
tm3_vidin_scl <= 1'b1 ;
|
||
|
|
end
|
||
|
|
7'b1000000 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicdata[4] ;
|
||
|
|
tm3_vidin_scl <= 1'b0 ;
|
||
|
|
end
|
||
|
|
7'b1000001 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicdata[3] ;
|
||
|
|
tm3_vidin_scl <= 1'b0 ;
|
||
|
|
end
|
||
|
|
7'b1000010 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicdata[3] ;
|
||
|
|
tm3_vidin_scl <= 1'b1 ;
|
||
|
|
end
|
||
|
|
7'b1000011 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicdata[3] ;
|
||
|
|
tm3_vidin_scl <= 1'b0 ;
|
||
|
|
end
|
||
|
|
7'b1000100 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicdata[2] ;
|
||
|
|
tm3_vidin_scl <= 1'b0 ;
|
||
|
|
end
|
||
|
|
7'b1000101 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicdata[2] ;
|
||
|
|
tm3_vidin_scl <= 1'b1 ;
|
||
|
|
end
|
||
|
|
7'b1000110 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicdata[2] ;
|
||
|
|
tm3_vidin_scl <= 1'b0 ;
|
||
|
|
end
|
||
|
|
7'b1000111 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicdata[1] ;
|
||
|
|
tm3_vidin_scl <= 1'b0 ;
|
||
|
|
end
|
||
|
|
7'b1001000 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicdata[1] ;
|
||
|
|
tm3_vidin_scl <= 1'b1 ;
|
||
|
|
end
|
||
|
|
7'b1001001 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicdata[1] ;
|
||
|
|
tm3_vidin_scl <= 1'b0 ;
|
||
|
|
end
|
||
|
|
7'b1001010 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicdata[0] ;
|
||
|
|
tm3_vidin_scl <= 1'b0 ;
|
||
|
|
end
|
||
|
|
7'b1001011 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicdata[0] ;
|
||
|
|
tm3_vidin_scl <= 1'b1 ;
|
||
|
|
end
|
||
|
|
7'b1001100 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= iicdata[0] ;
|
||
|
|
tm3_vidin_scl <= 1'b0 ;
|
||
|
|
end
|
||
|
|
7'b1001101 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= 1'b0 ;
|
||
|
|
tm3_vidin_scl <= 1'b0 ;
|
||
|
|
end
|
||
|
|
7'b1001110 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= 1'b0 ;
|
||
|
|
tm3_vidin_scl <= 1'b1 ;
|
||
|
|
end
|
||
|
|
7'b1001111 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= 1'b0 ;
|
||
|
|
tm3_vidin_scl <= 1'b0 ;
|
||
|
|
end
|
||
|
|
7'b1010000 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b0 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= 1'b0 ;
|
||
|
|
tm3_vidin_scl <= 1'b1 ;
|
||
|
|
end
|
||
|
|
7'b1010001 :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b1 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= 1'b1 ;
|
||
|
|
tm3_vidin_scl <= 1'b1 ;
|
||
|
|
end
|
||
|
|
default :
|
||
|
|
begin
|
||
|
|
iic_stop <= 1'b1 ;
|
||
|
|
tm3_vidin_sda_xhdl0 <= 1'b1 ;
|
||
|
|
tm3_vidin_scl <= 1'b1 ;
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
always @(reg_prog_state or iic_stop)
|
||
|
|
begin
|
||
|
|
case (reg_prog_state)
|
||
|
|
reg_prog1 :
|
||
|
|
begin
|
||
|
|
rst_done = 1'b1 ;
|
||
|
|
iicaddr = 8'b00000000 ;
|
||
|
|
iicdata = 8'b00000000 ;
|
||
|
|
iic_start = 1'b1 ;
|
||
|
|
if (iic_stop == 1'b0)
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog2 ;
|
||
|
|
end
|
||
|
|
else
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog1 ;
|
||
|
|
end
|
||
|
|
|
||
|
|
end
|
||
|
|
reg_prog2 :
|
||
|
|
begin
|
||
|
|
iicaddr = 8'b00000010 ;
|
||
|
|
iicdata = {5'b11000, 3'b000} ;
|
||
|
|
iic_start = 1'b0 ;
|
||
|
|
if (iic_stop == 1'b1)
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog3 ;
|
||
|
|
end
|
||
|
|
else
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog2 ;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
reg_prog3 :
|
||
|
|
begin
|
||
|
|
iicaddr = 8'b00000000 ;
|
||
|
|
iicdata = 8'b00000000 ;
|
||
|
|
iic_start = 1'b1 ;
|
||
|
|
if (iic_stop == 1'b0)
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog4 ;
|
||
|
|
end
|
||
|
|
else
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog3 ;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
reg_prog4 :
|
||
|
|
begin
|
||
|
|
iicaddr = 8'b00000011 ;
|
||
|
|
iicdata = 8'b00100011 ;
|
||
|
|
iic_start = 1'b0 ;
|
||
|
|
if (iic_stop == 1'b1)
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog5 ;
|
||
|
|
end
|
||
|
|
else
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog4 ;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
reg_prog5 :
|
||
|
|
begin
|
||
|
|
iicaddr = 8'b00000000 ;
|
||
|
|
iicdata = 8'b00000000 ;
|
||
|
|
iic_start = 1'b1 ;
|
||
|
|
if (iic_stop == 1'b0)
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog6 ;
|
||
|
|
end
|
||
|
|
else
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog5 ;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
reg_prog6 :
|
||
|
|
begin
|
||
|
|
iicaddr = 8'b00000110 ;
|
||
|
|
iicdata = 8'b11101011 ;
|
||
|
|
iic_start = 1'b0 ;
|
||
|
|
if (iic_stop == 1'b1)
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog7 ;
|
||
|
|
end
|
||
|
|
else
|
||
|
|
begin
|
||
|
|
|
||
|
|
reg_prog_nextstate = reg_prog6 ;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
reg_prog7 :
|
||
|
|
begin
|
||
|
|
iicaddr = 8'b00000000 ;
|
||
|
|
iicdata = 8'b00000000 ;
|
||
|
|
iic_start = 1'b1 ;
|
||
|
|
if (iic_stop == 1'b0)
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog8 ;
|
||
|
|
end
|
||
|
|
else
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog7 ;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
reg_prog8 :
|
||
|
|
begin
|
||
|
|
iicaddr = 8'b00000111 ;
|
||
|
|
iicdata = 8'b11100000 ;
|
||
|
|
iic_start = 1'b0 ;
|
||
|
|
if (iic_stop == 1'b1)
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog9 ;
|
||
|
|
end
|
||
|
|
else
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog8 ;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
reg_prog9 :
|
||
|
|
begin
|
||
|
|
iicaddr = 8'b00000000 ;
|
||
|
|
iicdata = 8'b00000000 ;
|
||
|
|
iic_start = 1'b1 ;
|
||
|
|
if (iic_stop == 1'b0)
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog10 ;
|
||
|
|
end
|
||
|
|
else
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog9 ;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
reg_prog10 :
|
||
|
|
begin
|
||
|
|
iicaddr = 8'b00001000 ;
|
||
|
|
iicdata = 8'b10000000 ;
|
||
|
|
iic_start = 1'b0 ;
|
||
|
|
if (iic_stop == 1'b1)
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog11 ;
|
||
|
|
end
|
||
|
|
else
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog10 ;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
reg_prog11 :
|
||
|
|
begin
|
||
|
|
iicaddr = 8'b00000000 ;
|
||
|
|
iicdata = 8'b00000000 ;
|
||
|
|
iic_start = 1'b1 ;
|
||
|
|
if (iic_stop == 1'b0)
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog12 ;
|
||
|
|
end
|
||
|
|
|
||
|
|
else
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog11 ;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
reg_prog12 :
|
||
|
|
begin
|
||
|
|
iicaddr = 8'b00001001 ;
|
||
|
|
iicdata = 8'b00000001 ;
|
||
|
|
iic_start = 1'b0 ;
|
||
|
|
if (iic_stop == 1'b1)
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog13 ;
|
||
|
|
end
|
||
|
|
else
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog12 ;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
reg_prog13 :
|
||
|
|
begin
|
||
|
|
iicaddr = 8'b00000000 ;
|
||
|
|
iicdata = 8'b00000000 ;
|
||
|
|
iic_start = 1'b1 ;
|
||
|
|
if (iic_stop == 1'b0)
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog14 ;
|
||
|
|
end
|
||
|
|
else
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog13 ;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
reg_prog14 :
|
||
|
|
begin
|
||
|
|
iicaddr = 8'b00001010 ;
|
||
|
|
iicdata = 8'b10000000 ;
|
||
|
|
iic_start = 1'b0 ;
|
||
|
|
if (iic_stop == 1'b1)
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog15 ;
|
||
|
|
end
|
||
|
|
else
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog14 ;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
reg_prog15 :
|
||
|
|
begin
|
||
|
|
iicaddr = 8'b00000000 ;
|
||
|
|
iicdata = 8'b00000000 ;
|
||
|
|
iic_start = 1'b1 ;
|
||
|
|
if (iic_stop == 1'b0)
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog16 ;
|
||
|
|
end
|
||
|
|
else
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog15 ;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
reg_prog16 :
|
||
|
|
begin
|
||
|
|
iicaddr = 8'b00001011 ;
|
||
|
|
iicdata = 8'b01000111 ;
|
||
|
|
iic_start = 1'b0 ;
|
||
|
|
if (iic_stop == 1'b1)
|
||
|
|
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog17 ;
|
||
|
|
end
|
||
|
|
else
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog16 ;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
reg_prog17 :
|
||
|
|
begin
|
||
|
|
iicaddr = 8'b00000000 ;
|
||
|
|
iicdata = 8'b00000000 ;
|
||
|
|
iic_start = 1'b1 ;
|
||
|
|
if (iic_stop == 1'b0)
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog18 ;
|
||
|
|
end
|
||
|
|
else
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog17 ;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
reg_prog18 :
|
||
|
|
begin
|
||
|
|
iicaddr = 8'b00001100 ;
|
||
|
|
iicdata = 8'b01000000 ;
|
||
|
|
iic_start = 1'b0 ;
|
||
|
|
if (iic_stop == 1'b1)
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog19 ;
|
||
|
|
end
|
||
|
|
else
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog18 ;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
reg_prog19 :
|
||
|
|
begin
|
||
|
|
iicaddr = 8'b00000000 ;
|
||
|
|
iicdata = 8'b00000000 ;
|
||
|
|
iic_start = 1'b1 ;
|
||
|
|
if (iic_stop == 1'b0)
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog20 ;
|
||
|
|
end
|
||
|
|
else
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog19 ;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
reg_prog20 :
|
||
|
|
begin
|
||
|
|
iicaddr = 8'b00001110 ;
|
||
|
|
iicdata = 8'b00000001 ;
|
||
|
|
iic_start = 1'b0 ;
|
||
|
|
if (iic_stop == 1'b1)
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog21 ;
|
||
|
|
end
|
||
|
|
else
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog20 ;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
reg_prog21 :
|
||
|
|
begin
|
||
|
|
iicaddr = 8'b00000000 ;
|
||
|
|
iicdata = 8'b00000000 ;
|
||
|
|
iic_start = 1'b1 ;
|
||
|
|
if (iic_stop == 1'b0)
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog22 ;
|
||
|
|
end
|
||
|
|
else
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog21 ;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
reg_prog22 :
|
||
|
|
begin
|
||
|
|
iicaddr = 8'b00010000 ;
|
||
|
|
iicdata = 8'b00000000 ;
|
||
|
|
iic_start = 1'b0 ;
|
||
|
|
if (iic_stop == 1'b1)
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog23 ;
|
||
|
|
end
|
||
|
|
else
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog22 ;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
reg_prog23 :
|
||
|
|
begin
|
||
|
|
iicaddr = 8'b00000000 ;
|
||
|
|
iicdata = 8'b00000000 ;
|
||
|
|
iic_start = 1'b1 ;
|
||
|
|
if (iic_stop == 1'b0)
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog24 ;
|
||
|
|
end
|
||
|
|
else
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog23 ;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
reg_prog24 :
|
||
|
|
begin
|
||
|
|
iicaddr = 8'b00010001 ;
|
||
|
|
iicdata = 8'b00011100 ;
|
||
|
|
iic_start = 1'b0 ;
|
||
|
|
if (iic_stop == 1'b1)
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog25 ;
|
||
|
|
end
|
||
|
|
else
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog24 ;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
reg_prog25 :
|
||
|
|
begin
|
||
|
|
iicaddr = 8'b00000000 ;
|
||
|
|
iicdata = 8'b00000000 ;
|
||
|
|
iic_start = 1'b1 ;
|
||
|
|
if (iic_stop == 1'b0)
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog26 ;
|
||
|
|
end
|
||
|
|
else
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog25 ;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
reg_prog26 :
|
||
|
|
begin
|
||
|
|
iicaddr = 8'b00010010 ;
|
||
|
|
iicdata = 8'b00001001 ;
|
||
|
|
iic_start = 1'b0 ;
|
||
|
|
if (iic_stop == 1'b1)
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog_end ;
|
||
|
|
end
|
||
|
|
else
|
||
|
|
begin
|
||
|
|
reg_prog_nextstate = reg_prog26 ;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
reg_prog_end :
|
||
|
|
begin
|
||
|
|
iicaddr = 8'b00000000 ;
|
||
|
|
iicdata = 8'b00000000 ;
|
||
|
|
iic_start = 1'b0 ;
|
||
|
|
reg_prog_nextstate = reg_prog_end ;
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
always @(posedge tm3_clk_v2)
|
||
|
|
begin
|
||
|
|
if (rst_done == 1'b1)
|
||
|
|
begin
|
||
|
|
rst <= 1'b1 ;
|
||
|
|
end
|
||
|
|
temp_reg1 <= tm3_vidin_rts0 ;
|
||
|
|
temp_reg2 <= temp_reg1 ;
|
||
|
|
if (rst == 1'b0)
|
||
|
|
begin
|
||
|
|
reg_prog_state <= reg_prog1 ;
|
||
|
|
end
|
||
|
|
else if ((temp_reg1 == 1'b0) & (temp_reg2 == 1'b1))
|
||
|
|
begin
|
||
|
|
reg_prog_state <= reg_prog1 ;
|
||
|
|
end
|
||
|
|
else
|
||
|
|
begin
|
||
|
|
reg_prog_state <= reg_prog_nextstate ;
|
||
|
|
end
|
||
|
|
if (iic_stop == 1'b0)
|
||
|
|
begin
|
||
|
|
iic_state <= iic_state + 1 ;
|
||
|
|
end
|
||
|
|
else if (iic_start == 1'b1)
|
||
|
|
begin
|
||
|
|
iic_state <= 7'b0000001 ;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
endmodule
|
||
|
|
|
||
|
|
|
||
|
|
|