OpenFPGA/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v

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2020-04-20 14:37:39 -05:00
/////////////////////////////////////////
// Functionality: 2-input AND
// Author: Xifan Tang
////////////////////////////////////////
`timescale 1ns / 1ps
module and2(
a,
b,
c);
input wire a;
input wire b;
output wire c;
assign c = a & b;
endmodule