OpenFPGA/openfpga_flow/benchmarks/mcnc_big20/s298/s298.v

/* Generated by Yosys 0.8+133 (git sha1 2a2e0a4, gcc 7.3.0 -fPIC -Os) */

module s298(clock, G0, G1, G2, G117, G132, G66, G118, G133, G67);
  input G0;
  input G1;
  (* init = 1'h0 *)
  reg G10 = 1'h0;
  (* init = 1'h0 *)
  reg G11 = 1'h0;
  (* init = 1'h0 *)
  output G117;
  reg G117 = 1'h0;
  (* init = 1'h0 *)
  output G118;
  reg G118 = 1'h0;
  (* init = 1'h0 *)
  reg G12 = 1'h0;
  (* init = 1'h0 *)
  reg G13 = 1'h0;
  (* init = 1'h0 *)
  output G132;
  reg G132 = 1'h0;
  (* init = 1'h0 *)
  output G133;
  reg G133 = 1'h0;
  (* init = 1'h0 *)
  reg G14 = 1'h0;
  (* init = 1'h0 *)
  reg G15 = 1'h0;
  input G2;
  (* init = 1'h0 *)
  reg G22 = 1'h0;
  (* init = 1'h0 *)
  reg G23 = 1'h0;
  (* init = 1'h0 *)
  output G66;
  reg G66 = 1'h0;
  (* init = 1'h0 *)
  output G67;
  reg G67 = 1'h0;
  input clock;
  wire n21;
  wire n26;
  wire n31;
  wire n36;
  wire n41;
  wire n46;
  wire n51;
  wire n55;
  wire n56;
  wire n57;
  wire n59;
  wire n59_1;
  wire n63;
  wire n65;
  wire n67;
  wire n71;
  wire n75;
  wire n80;
  always @(posedge clock)
      G10 <= n21;
  always @(posedge clock)
      G118 <= n63;
  always @(posedge clock)
      G132 <= n67;
  always @(posedge clock)
      G133 <= n71;
  always @(posedge clock)
      G22 <= n75;
  always @(posedge clock)
      G23 <= n80;
  always @(posedge clock)
      G11 <= n26;
  always @(posedge clock)
      G12 <= n31;
  always @(posedge clock)
      G13 <= n36;
  always @(posedge clock)
      G14 <= n41;
  always @(posedge clock)
      G15 <= n46;
  always @(posedge clock)
      G66 <= n51;
  always @(posedge clock)
      G67 <= n55;
  always @(posedge clock)
      G117 <= n59;
  assign n63 = 8'h8d >> { G10, n57, n56 };
  assign n56 = 64'h55555555555545d5 >> { G12, G14, G22, G13, G11, G15 };
  assign n57 = 32'd3963940422 >> { G11, G118, G12, G13, G14 };
  assign n67 = 8'h8d >> { G10, n59_1, n56 };
  assign n59_1 = 32'd2818615810 >> { G11, G132, G12, G13, G14 };
  assign n21 = 4'h1 >> { G10, G0 };
  assign n26 = 32'd100926982 >> { G13, G12, G0, G11, G10 };
  assign n31 = 16'h1222 >> { G10, G11, G0, G12 };
  assign n36 = 32'd304095778 >> { G10, G12, G11, G0, G13 };
  assign n41 = 8'h09 >> { G0, G14, n65 };
  assign n65 = 32'd1431655701 >> { G12, G11, G13, G10, G23 };
  assign n46 = 4'h1 >> { n56, G0 };
  assign n51 = 32'd2323679744 >> { G12, G13, G14, G66, n56 };
  assign n55 = 64'ha0a20002a2822202 >> { G12, G67, G11, G14, G13, n56 };
  assign n59 = 64'ha022a222a0228022 >> { G11, G12, G14, G117, G13, n56 };
  assign n71 = 64'h88a0002088800000 >> { G11, G133, G13, G12, G14, n56 };
  assign n75 = 8'h06 >> { G0, G22, G2 };
  assign n80 = 8'h06 >> { G0, G23, G1 };
endmodule