516 lines
12 KiB
Coq
516 lines
12 KiB
Coq
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Generic Dual-Port Synchronous RAM ////
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//// ////
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//// This file is part of memory library available from ////
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//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
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//// ////
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//// Description ////
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//// This block is a wrapper with common dual-port ////
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//// synchronous memory interface for different ////
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//// types of ASIC and FPGA RAMs. Beside universal memory ////
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//// interface it also provides behavioral model of generic ////
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//// dual-port synchronous RAM. ////
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//// It also contains a fully synthesizeable model for FPGAs. ////
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//// It should be used in all OPENCORES designs that want to be ////
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//// portable accross different target technologies and ////
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//// independent of target memory. ////
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//// ////
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//// Supported ASIC RAMs are: ////
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//// - Artisan Dual-Port Sync RAM ////
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//// - Avant! Two-Port Sync RAM (*) ////
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//// - Virage 2-port Sync RAM ////
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//// ////
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//// Supported FPGA RAMs are: ////
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//// - Generic FPGA (VENDOR_FPGA) ////
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//// Tested RAMs: Altera, Xilinx ////
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//// Synthesis tools: LeonardoSpectrum, Synplicity ////
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//// - Xilinx (VENDOR_XILINX) ////
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//// - Altera (VENDOR_ALTERA) ////
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//// ////
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//// To Do: ////
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//// - fix Avant! ////
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//// - add additional RAMs (VS etc) ////
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//// ////
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//// Author(s): ////
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//// - Richard Herveille, richard@asics.ws ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: generic_dpram.v,v $
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// Revision 1.3 2003/03/18 21:45:48 rherveille
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// Added WISHBONE revB.3 Registered Feedback Cycles support
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//
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// Revision 1.4 2002/09/28 08:18:52 rherveille
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// Changed synthesizeable FPGA memory implementation.
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// Fixed some issues with Xilinx BlockRAM
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//
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// Revision 1.3 2001/11/09 00:34:18 samg
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// minor changes: unified with all common rams
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//
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// Revision 1.2 2001/11/08 19:11:31 samg
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// added valid checks to behvioral model
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//
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// Revision 1.1.1.1 2001/09/14 09:57:10 rherveille
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// Major cleanup.
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// Files are now compliant to Altera & Xilinx memories.
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// Memories are now compatible, i.e. drop-in replacements.
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// Added synthesizeable generic FPGA description.
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// Created "generic_memories" cvs entry.
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//
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// Revision 1.1.1.2 2001/08/21 13:09:27 damjan
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// *** empty log message ***
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//
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// Revision 1.1 2001/08/20 18:23:20 damjan
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// Initial revision
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//
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// Revision 1.1 2001/08/09 13:39:33 lampret
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// Major clean-up.
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//
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// Revision 1.2 2001/07/30 05:38:02 lampret
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// Adding empty directories required by HDL coding guidelines
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//
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//
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//synopsys translate_off
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`include "timescale.v"
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//synopsys translate_on
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`define VENDOR_FPGA
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//`define VENDOR_XILINX
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//`define VENDOR_ALTERA
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module generic_dpram(
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// Generic synchronous dual-port RAM interface
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rclk, rrst, rce, oe, raddr, do,
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wclk, wrst, wce, we, waddr, di
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);
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//
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// Default address and data buses width
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//
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parameter aw = 5; // number of bits in address-bus
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parameter dw = 16; // number of bits in data-bus
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//
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// Generic synchronous double-port RAM interface
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//
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// read port
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input rclk; // read clock, rising edge trigger
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input rrst; // read port reset, active high
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input rce; // read port chip enable, active high
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input oe; // output enable, active high
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input [aw-1:0] raddr; // read address
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output [dw-1:0] do; // data output
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// write port
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input wclk; // write clock, rising edge trigger
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input wrst; // write port reset, active high
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input wce; // write port chip enable, active high
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input we; // write enable, active high
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input [aw-1:0] waddr; // write address
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input [dw-1:0] di; // data input
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//
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// Module body
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//
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`ifdef VENDOR_FPGA
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//
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// Instantiation synthesizeable FPGA memory
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//
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// This code has been tested using LeonardoSpectrum and Synplicity.
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// The code correctly instantiates Altera EABs and Xilinx BlockRAMs.
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//
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// NOTE:
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// 'synthesis syn_ramstyle="block_ram"' is a Synplify attribute.
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// It instructs Synplify to map to BlockRAMs instead of the default SelectRAMs
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reg [dw-1:0] mem [(1<<aw) -1:0] /* synthesis syn_ramstyle="block_ram" */;
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reg [aw-1:0] ra; // register read address
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// read operation
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always @(posedge rclk)
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if (rce)
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ra <= #1 raddr;
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assign do = mem[ra];
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// write operation
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always @(posedge wclk)
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if (we && wce)
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mem[waddr] <= #1 di;
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`else
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`ifdef VENDOR_XILINX
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//
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// Instantiation of FPGA memory:
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//
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// Virtex/Spartan2 BlockRAMs
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//
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xilinx_ram_dp xilinx_ram(
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// read port
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.CLKA(rclk),
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.RSTA(rrst),
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.ENA(rce),
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.ADDRA(raddr),
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.DIA( {dw{1'b0}} ),
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.WEA(1'b0),
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.DOA(do),
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// write port
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.CLKB(wclk),
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.RSTB(wrst),
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.ENB(wce),
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.ADDRB(waddr),
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.DIB(di),
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.WEB(we),
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.DOB()
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);
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defparam
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xilinx_ram.dwidth = dw,
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xilinx_ram.awidth = aw;
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`else
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`ifdef VENDOR_ALTERA
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//
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// Instantiation of FPGA memory:
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//
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// Altera FLEX/APEX EABs
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//
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altera_ram_dp altera_ram(
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// read port
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.rdclock(rclk),
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.rdclocken(rce),
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.rdaddress(raddr),
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.q(do),
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// write port
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.wrclock(wclk),
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.wrclocken(wce),
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.wren(we),
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.wraddress(waddr),
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.data(di)
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);
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defparam
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altera_ram.dwidth = dw,
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altera_ram.awidth = aw;
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`else
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`ifdef VENDOR_ARTISAN
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//
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// Instantiation of ASIC memory:
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//
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// Artisan Synchronous Double-Port RAM (ra2sh)
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//
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art_hsdp #(dw, 1<<aw, aw) artisan_sdp(
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// read port
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.qa(do),
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.clka(rclk),
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.cena(~rce),
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.wena(1'b1),
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.aa(raddr),
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.da( {dw{1'b0}} ),
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.oena(~oe),
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// write port
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.qb(),
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.clkb(wclk),
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.cenb(~wce),
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.wenb(~we),
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.ab(waddr),
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.db(di),
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.oenb(1'b1)
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);
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`else
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`ifdef VENDOR_AVANT
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//
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// Instantiation of ASIC memory:
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//
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// Avant! Asynchronous Two-Port RAM
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//
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avant_atp avant_atp(
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.web(~we),
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.reb(),
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.oeb(~oe),
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.rcsb(),
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.wcsb(),
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.ra(raddr),
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.wa(waddr),
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.di(di),
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.do(do)
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);
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`else
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`ifdef VENDOR_VIRAGE
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//
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// Instantiation of ASIC memory:
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//
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// Virage Synchronous 2-port R/W RAM
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//
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virage_stp virage_stp(
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// read port
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.CLKA(rclk),
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.MEA(rce_a),
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.ADRA(raddr),
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.DA( {dw{1'b0}} ),
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.WEA(1'b0),
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.OEA(oe),
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.QA(do),
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// write port
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.CLKB(wclk),
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.MEB(wce),
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.ADRB(waddr),
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.DB(di),
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.WEB(we),
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.OEB(1'b1),
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.QB()
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);
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`else
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//
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// Generic dual-port synchronous RAM model
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//
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//
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// Generic RAM's registers and wires
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//
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reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
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reg [dw-1:0] do_reg; // RAM data output register
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//
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// Data output drivers
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//
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assign do = (oe & rce) ? do_reg : {dw{1'bz}};
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// read operation
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always @(posedge rclk)
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if (rce)
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do_reg <= #1 (we && (waddr==raddr)) ? {dw{1'b x}} : mem[raddr];
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// write operation
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always @(posedge wclk)
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if (wce && we)
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mem[waddr] <= #1 di;
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// Task prints range of memory
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// *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.
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task print_ram;
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input [aw-1:0] start;
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input [aw-1:0] finish;
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integer rnum;
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begin
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for (rnum=start;rnum<=finish;rnum=rnum+1)
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$display("Addr %h = %h",rnum,mem[rnum]);
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end
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endtask
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`endif // !VENDOR_VIRAGE
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`endif // !VENDOR_AVANT
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`endif // !VENDOR_ARTISAN
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`endif // !VENDOR_ALTERA
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`endif // !VENDOR_XILINX
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`endif // !VENDOR_FPGA
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endmodule
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//
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// Black-box modules
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//
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`ifdef VENDOR_ALTERA
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module altera_ram_dp(
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data,
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wraddress,
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rdaddress,
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wren,
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wrclock,
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wrclocken,
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rdclock,
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rdclocken,
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q) /* synthesis black_box */;
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|
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parameter awidth = 7;
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parameter dwidth = 8;
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input [dwidth -1:0] data;
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input [awidth -1:0] wraddress;
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input [awidth -1:0] rdaddress;
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input wren;
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input wrclock;
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input wrclocken;
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input rdclock;
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input rdclocken;
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output [dwidth -1:0] q;
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|
|
|
||
|
|
// synopsis translate_off
|
||
|
|
// exemplar translate_off
|
||
|
|
|
||
|
|
syn_dpram_rowr #(
|
||
|
|
"UNUSED",
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||
|
|
dwidth,
|
||
|
|
awidth,
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||
|
|
1 << awidth
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||
|
|
)
|
||
|
|
altera_dpram_model (
|
||
|
|
// read port
|
||
|
|
.RdClock(rdclock),
|
||
|
|
.RdClken(rdclocken),
|
||
|
|
.RdAddress(rdaddress),
|
||
|
|
.RdEn(1'b1),
|
||
|
|
.Q(q),
|
||
|
|
|
||
|
|
// write port
|
||
|
|
.WrClock(wrclock),
|
||
|
|
.WrClken(wrclocken),
|
||
|
|
.WrAddress(wraddress),
|
||
|
|
.WrEn(wren),
|
||
|
|
.Data(data)
|
||
|
|
);
|
||
|
|
|
||
|
|
// exemplar translate_on
|
||
|
|
// synopsis translate_on
|
||
|
|
|
||
|
|
endmodule
|
||
|
|
`endif // VENDOR_ALTERA
|
||
|
|
|
||
|
|
`ifdef VENDOR_XILINX
|
||
|
|
module xilinx_ram_dp (
|
||
|
|
ADDRA,
|
||
|
|
CLKA,
|
||
|
|
ADDRB,
|
||
|
|
CLKB,
|
||
|
|
DIA,
|
||
|
|
WEA,
|
||
|
|
DIB,
|
||
|
|
WEB,
|
||
|
|
ENA,
|
||
|
|
ENB,
|
||
|
|
RSTA,
|
||
|
|
RSTB,
|
||
|
|
DOA,
|
||
|
|
DOB) /* synthesis black_box */ ;
|
||
|
|
|
||
|
|
parameter awidth = 7;
|
||
|
|
parameter dwidth = 8;
|
||
|
|
|
||
|
|
// port_a
|
||
|
|
input CLKA;
|
||
|
|
input RSTA;
|
||
|
|
input ENA;
|
||
|
|
input [awidth-1:0] ADDRA;
|
||
|
|
input [dwidth-1:0] DIA;
|
||
|
|
input WEA;
|
||
|
|
output [dwidth-1:0] DOA;
|
||
|
|
|
||
|
|
// port_b
|
||
|
|
input CLKB;
|
||
|
|
input RSTB;
|
||
|
|
input ENB;
|
||
|
|
input [awidth-1:0] ADDRB;
|
||
|
|
input [dwidth-1:0] DIB;
|
||
|
|
input WEB;
|
||
|
|
output [dwidth-1:0] DOB;
|
||
|
|
|
||
|
|
// insert simulation model
|
||
|
|
|
||
|
|
|
||
|
|
// synopsys translate_off
|
||
|
|
// exemplar translate_off
|
||
|
|
|
||
|
|
C_MEM_DP_BLOCK_V1_0 #(
|
||
|
|
awidth,
|
||
|
|
awidth,
|
||
|
|
1,
|
||
|
|
1,
|
||
|
|
"0",
|
||
|
|
1 << awidth,
|
||
|
|
1 << awidth,
|
||
|
|
1,
|
||
|
|
1,
|
||
|
|
1,
|
||
|
|
1,
|
||
|
|
1,
|
||
|
|
1,
|
||
|
|
1,
|
||
|
|
1,
|
||
|
|
1,
|
||
|
|
1,
|
||
|
|
1,
|
||
|
|
1,
|
||
|
|
1,
|
||
|
|
"",
|
||
|
|
16,
|
||
|
|
0,
|
||
|
|
0,
|
||
|
|
1,
|
||
|
|
1,
|
||
|
|
1,
|
||
|
|
1,
|
||
|
|
dwidth,
|
||
|
|
dwidth)
|
||
|
|
xilinx_dpram_model (
|
||
|
|
.ADDRA(ADDRA),
|
||
|
|
.CLKA(CLKA),
|
||
|
|
.ADDRB(ADDRB),
|
||
|
|
.CLKB(CLKB),
|
||
|
|
.DIA(DIA),
|
||
|
|
.WEA(WEA),
|
||
|
|
.DIB(DIB),
|
||
|
|
.WEB(WEB),
|
||
|
|
.ENA(ENA),
|
||
|
|
.ENB(ENB),
|
||
|
|
.RSTA(RSTA),
|
||
|
|
.RSTB(RSTB),
|
||
|
|
.DOA(DOA),
|
||
|
|
.DOB(DOB));
|
||
|
|
|
||
|
|
// exemplar translate_on
|
||
|
|
// synopsys translate_on
|
||
|
|
|
||
|
|
endmodule
|
||
|
|
`endif // VENDOR_XILINX
|