OpenFPGA/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml

<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework
     This annotation supports the k6_N10_40nm.xml 
     - General purpose logic block
       - K = 6, N = 10, I = 40
       - Single mode
     - Routing architecture
       - L = 4, fc_in = 0.15, fc_out = 0.1
  -->
<openfpga_architecture>
  <technology_library>
    <device_library>
      <device_model name="logic" type="transistor">
        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
        <design vdd="0.9" pn_ratio="2"/>
        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
      </device_model>
      <device_model name="io" type="transistor">
        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
        <design vdd="2.5" pn_ratio="3"/>
        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
      </device_model>
    </device_library>
    <variation_library>
      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
    </variation_library>
  </technology_library>
  <circuit_library>
    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
      <design_technology type="cmos" topology="inverter" size="1"/>
      <device_technology device_model_name="logic"/>
      <port type="input" prefix="in" size="1"/>
      <port type="output" prefix="out" size="1"/>
      <delay_matrix type="rise" in_port="in" out_port="out">
        10e-12
      </delay_matrix>
      <delay_matrix type="fall" in_port="in" out_port="out">
        10e-12
      </delay_matrix>
    </circuit_model>
    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
      <device_technology device_model_name="logic"/>
      <port type="input" prefix="in" size="1"/>
      <port type="output" prefix="out" size="1"/>
      <delay_matrix type="rise" in_port="in" out_port="out">
        10e-12
      </delay_matrix>
      <delay_matrix type="fall" in_port="in" out_port="out">
        10e-12
      </delay_matrix>
    </circuit_model>
    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
      <device_technology device_model_name="logic"/>
      <port type="input" prefix="in" size="1"/>
      <port type="output" prefix="out" size="1"/>
      <delay_matrix type="rise" in_port="in" out_port="out">
        10e-12
      </delay_matrix>
      <delay_matrix type="fall" in_port="in" out_port="out">
        10e-12
      </delay_matrix>
    </circuit_model>
    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
      <design_technology type="cmos" topology="OR"/>
      <device_technology device_model_name="logic"/>
      <input_buffer exist="false"/>
      <output_buffer exist="false"/>
      <port type="input" prefix="a" size="1"/>
      <port type="input" prefix="b" size="1"/>
      <port type="output" prefix="out" size="1"/>
      <delay_matrix type="rise" in_port="a b" out_port="out">
        10e-12 5e-12
      </delay_matrix>
      <delay_matrix type="fall" in_port="a b" out_port="out">
        10e-12 5e-12
      </delay_matrix>
    </circuit_model>
    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
      <device_technology device_model_name="logic"/>
      <input_buffer exist="false"/>
      <output_buffer exist="false"/>
      <port type="input" prefix="in" size="1"/>
      <port type="input" prefix="sel" size="1"/>
      <port type="input" prefix="selb" size="1"/>
      <port type="output" prefix="out" size="1"/>
      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
        10e-12 5e-12 5e-12
      </delay_matrix>
      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
        10e-12 5e-12 5e-12
      </delay_matrix>
    </circuit_model>
    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
      <design_technology type="cmos"/>
      <input_buffer exist="false"/>
      <output_buffer exist="false"/>
      <port type="input" prefix="in" size="1"/>
      <port type="output" prefix="out" size="1"/>
      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
      <!-- model_type could be T, res_val and cap_val DON'T CARE -->
    </circuit_model>
    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
      <design_technology type="cmos"/>
      <input_buffer exist="false"/>
      <output_buffer exist="false"/>
      <port type="input" prefix="in" size="1"/>
      <port type="output" prefix="out" size="1"/>
      <wire_param model_type="pi" R="0" C="0" num_level="1"/>
      <!-- model_type could be T, res_val cap_val should be defined -->
    </circuit_model>
    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
      <input_buffer exist="true" circuit_model_name="INVTX1"/>
      <output_buffer exist="true" circuit_model_name="INVTX1"/>
      <pass_gate_logic circuit_model_name="TGATE"/>
      <port type="input" prefix="in" size="1"/>
      <port type="output" prefix="out" size="1"/>
      <port type="sram" prefix="sram" size="1"/>
    </circuit_model>
    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
      <input_buffer exist="true" circuit_model_name="INVTX1"/>
      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
      <pass_gate_logic circuit_model_name="TGATE"/>
      <port type="input" prefix="in" size="1"/>
      <port type="output" prefix="out" size="1"/>
      <port type="sram" prefix="sram" size="1"/>
    </circuit_model>
    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
      <input_buffer exist="true" circuit_model_name="INVTX1"/>
      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
      <pass_gate_logic circuit_model_name="TGATE"/>
      <port type="input" prefix="in" size="1"/>
      <port type="output" prefix="out" size="1"/>
      <port type="sram" prefix="sram" size="1"/>
    </circuit_model>
    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
      <design_technology type="cmos"/>
      <input_buffer exist="true" circuit_model_name="INVTX1"/>
      <output_buffer exist="true" circuit_model_name="INVTX1"/>
      <port type="input" prefix="D" size="1"/>
      <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
      <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
      <port type="output" prefix="Q" size="1"/>
      <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
    </circuit_model>
    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
      <design_technology type="cmos" fracturable_lut="true"/>
      <input_buffer exist="true" circuit_model_name="INVTX1"/>
      <output_buffer exist="true" circuit_model_name="INVTX1"/>
      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
      <pass_gate_logic circuit_model_name="TGATE"/>
      <port type="input" prefix="in" size="6" tri_state_map="-----1" circuit_model_name="OR2"/>
      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
      <port type="sram" prefix="sram" size="64"/>
      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
    </circuit_model>
    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
    <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
      <design_technology type="cmos"/>
      <input_buffer exist="true" circuit_model_name="INVTX1"/>
      <output_buffer exist="true" circuit_model_name="INVTX1"/>
      <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
      <port type="input" prefix="D" size="1"/>
      <port type="output" prefix="Q" size="1"/>
      <port type="output" prefix="QN" size="1"/>
      <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
    </circuit_model>
    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
      <design_technology type="cmos"/>
      <input_buffer exist="true" circuit_model_name="INVTX1"/>
      <output_buffer exist="true" circuit_model_name="INVTX1"/>
      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
      <port type="input" prefix="outpad" lib_name="A" size="1"/>
      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
    </circuit_model>
  </circuit_library>
  <configuration_protocol>
    <organization type="scan_chain" circuit_model_name="DFFR"/>
  </configuration_protocol>
  <connection_block>
    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
  </connection_block>
  <switch_block>
    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
  </switch_block>
  <routing_segment>
    <segment name="L4" circuit_model_name="chan_segment"/>
  </routing_segment>
  <pb_type_annotations>
    <!-- physical pb_type binding in complex block IO -->
    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/>
    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
    <!-- End physical pb_type binding in complex block IO -->
    <!-- physical pb_type binding in complex block CLB -->
    <!-- physical mode will be the default mode if not specified -->
    <pb_type name="clb">
      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
    </pb_type>
    <pb_type name="clb.fle" physical_mode_name="physical"/>
    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="0"/>
    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/>
    <!-- Binding operating pb_type to physical pb_type -->
    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="1" physical_pb_type_index_factor="0.5">
      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
      <port name="in" physical_mode_port="in[0:4]"/>
      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
    </pb_type>
    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="0">
      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
      <port name="in" physical_mode_port="in[0:5]"/>
      <port name="out" physical_mode_port="lut6_out"/>
    </pb_type>
    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
    <!-- End physical pb_type binding in complex block IO -->
  </pb_type_annotations>
</openfpga_architecture>