466 lines
13 KiB
Coq
466 lines
13 KiB
Coq
|
//////////////////////////////////////////////////////////////////////
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//// ////
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//// Generic Two-Port Synchronous RAM ////
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//// ////
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//// This file is part of pci bridge project ////
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//// http://www.opencores.org/cvsweb.shtml/pci/ ////
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//// ////
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//// Description ////
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//// This block is a wrapper with common two-port ////
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//// synchronous memory interface for different ////
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//// types of ASIC and FPGA RAMs. Beside universal memory ////
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//// interface it also provides behavioral model of generic ////
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//// two-port synchronous RAM. ////
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//// It should be used in all OPENCORES designs that want to be ////
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//// portable accross different target technologies and ////
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//// independent of target memory. ////
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//// ////
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//// Supported ASIC RAMs are: ////
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//// - Artisan Double-Port Sync RAM ////
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//// - Avant! Two-Port Sync RAM (*) ////
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//// - Virage 2-port Sync RAM ////
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//// ////
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//// Supported FPGA RAMs are: ////
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//// - Xilinx Virtex RAMB4_S16_S16 ////
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//// ////
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//// To Do: ////
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//// - fix Avant! ////
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//// - xilinx rams need external tri-state logic ////
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//// - add additional RAMs (Altera, VS etc) ////
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//// ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Miha Dolenc, mihad@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: pci_wb_tpram.v,v $
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// Revision 1.4 2004/08/19 15:27:34 mihad
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// Changed minimum pci image size to 256 bytes because
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// of some PC system problems with size of IO images.
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//
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// Revision 1.3 2003/10/17 09:11:52 markom
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// mbist signals updated according to newest convention
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//
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// Revision 1.2 2003/08/14 13:06:03 simons
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// synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated.
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//
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// Revision 1.1 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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//
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// Revision 1.7 2002/10/18 03:36:37 tadejm
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// Changed wrong signal name mbist_sen into mbist_ctrl_i.
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//
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// Revision 1.6 2002/10/17 22:49:22 tadejm
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// Changed BIST signals for RAMs.
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//
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// Revision 1.5 2002/10/11 10:09:01 mihad
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// Added additional testcase and changed rst name in BIST to trst
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//
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// Revision 1.4 2002/10/08 17:17:06 mihad
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// Added BIST signals for RAMs.
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//
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// Revision 1.3 2002/09/30 17:22:27 mihad
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// Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!
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//
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// Revision 1.2 2002/08/19 16:51:36 mihad
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// Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives
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//
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// Revision 1.1 2002/02/01 14:43:31 mihad
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// *** empty log message ***
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "pci_constants.v"
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module pci_wb_tpram
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(
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// Generic synchronous two-port RAM interface
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clk_a,
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rst_a,
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ce_a,
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we_a,
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oe_a,
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addr_a,
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di_a,
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do_a,
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clk_b,
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rst_b,
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ce_b,
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we_b,
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oe_b,
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addr_b,
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di_b,
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do_b
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`ifdef PCI_BIST
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,
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// debug chain signals
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mbist_si_i, // bist scan serial in
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mbist_so_o, // bist scan serial out
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mbist_ctrl_i // bist chain shift control
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`endif
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);
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//
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// Default address and data buses width
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//
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parameter aw = 8;
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parameter dw = 40;
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//
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// Generic synchronous two-port RAM interface
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//
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input clk_a; // Clock
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input rst_a; // Reset
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input ce_a; // Chip enable input
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input we_a; // Write enable input
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input oe_a; // Output enable input
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input [aw-1:0] addr_a; // address bus inputs
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input [dw-1:0] di_a; // input data bus
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output [dw-1:0] do_a; // output data bus
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input clk_b; // Clock
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input rst_b; // Reset
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input ce_b; // Chip enable input
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input we_b; // Write enable input
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input oe_b; // Output enable input
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input [aw-1:0] addr_b; // address bus inputs
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input [dw-1:0] di_b; // input data bus
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output [dw-1:0] do_b; // output data bus
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`ifdef PCI_BIST
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// debug chain signals
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input mbist_si_i; // bist scan serial in
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output mbist_so_o; // bist scan serial out
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input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
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`endif
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//
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// Internal wires and registers
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//
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`ifdef WB_VS_STP
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`define PCI_WB_RAM_SELECTED
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`ifdef PCI_BIST
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vs_hdtp_64x40_bist i_vs_hdtp_64x40_bist
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`else
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vs_hdtp_64x40 i_vs_hdtp_64x40
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`endif
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(
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.RCK (clk_b),
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.WCK (clk_a),
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.RADR (addr_b),
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.WADR (addr_a),
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.DI (di_a),
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.DOUT (do_b),
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.REN (1'b0),
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.WEN (!we_a)
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`ifdef PCI_BIST
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,
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// debug chain signals
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.mbist_si_i (mbist_si_i),
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.mbist_so_o (mbist_so_o),
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.mbist_ctrl_i (mbist_ctrl_i)
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`endif
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);
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assign do_a = 0 ;
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`endif
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`ifdef WB_ARTISAN_SDP
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`define PCI_WB_RAM_SELECTED
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//
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// Instantiation of ASIC memory:
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//
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// Artisan Synchronous Double-Port RAM (ra2sh)
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//
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`ifdef PCI_BIST
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art_hsdp_64x40_bist /*#(dw, 1<<aw, aw) */ artisan_sdp
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(
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.QA(do_a),
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.CLKA(clk_a),
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.CENA(~ce_a),
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.WENA(~we_a),
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.AA(addr_a),
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.DA(di_a),
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.OENA(~oe_a),
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.QB(do_b),
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.CLKB(clk_b),
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.CENB(~ce_b),
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.WENB(~we_b),
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.AB(addr_b),
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.DB(di_b),
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.OENB(~oe_b),
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.mbist_si_i (mbist_si_i),
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.mbist_so_o (mbist_so_o),
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.mbist_ctrl_i (mbist_ctrl_i)
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);
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`else
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art_hsdp_64x40 /*#(dw, 1<<aw, aw) */ artisan_sdp
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(
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.QA(do_a),
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.CLKA(clk_a),
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.CENA(~ce_a),
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.WENA(~we_a),
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.AA(addr_a),
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.DA(di_a),
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.OENA(~oe_a),
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.QB(do_b),
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.CLKB(clk_b),
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.CENB(~ce_b),
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.WENB(~we_b),
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.AB(addr_b),
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.DB(di_b),
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.OENB(~oe_b)
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);
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`endif
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`endif
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`ifdef AVANT_ATP
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`define PCI_WB_RAM_SELECTED
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//
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// Instantiation of ASIC memory:
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//
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// Avant! Asynchronous Two-Port RAM
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//
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avant_atp avant_atp(
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.web(~we),
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.reb(),
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.oeb(~oe),
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.rcsb(),
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.wcsb(),
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.ra(addr),
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.wa(addr),
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.di(di),
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.do(do)
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);
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`endif
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`ifdef VIRAGE_STP
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`define PCI_WB_RAM_SELECTED
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//
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// Instantiation of ASIC memory:
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//
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// Virage Synchronous 2-port R/W RAM
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//
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virage_stp virage_stp(
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.QA(do_a),
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.QB(do_b),
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.ADRA(addr_a),
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.DA(di_a),
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.WEA(we_a),
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.OEA(oe_a),
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.MEA(ce_a),
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.CLKA(clk_a),
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.ADRB(adr_b),
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.DB(di_b),
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.WEB(we_b),
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.OEB(oe_b),
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.MEB(ce_b),
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.CLKB(clk_b)
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);
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`endif
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`ifdef WB_XILINX_DIST_RAM
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`define PCI_WB_RAM_SELECTED
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reg [(aw-1):0] out_address ;
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always@(posedge clk_b or posedge rst_b)
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begin
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if ( rst_b )
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out_address <= #1 0 ;
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else if (ce_b)
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out_address <= #1 addr_b ;
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end
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pci_ram_16x40d #(aw) wb_distributed_ram
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(
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.data_out (do_b),
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.we (we_a),
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.data_in (di_a),
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.read_address (out_address),
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.write_address (addr_a),
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.wclk (clk_a)
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);
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assign do_a = 0 ;
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`endif
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`ifdef WB_XILINX_RAMB4
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`define PCI_WB_RAM_SELECTED
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//
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// Instantiation of FPGA memory:
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//
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// Virtex/Spartan2
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//
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//
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// Block 0
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//
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RAMB4_S16_S16 ramb4_s16_s16_0(
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.CLKA(clk_a),
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.RSTA(rst_a),
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.ADDRA(addr_a),
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.DIA(di_a[15:0]),
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.ENA(ce_a),
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.WEA(we_a),
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.DOA(do_a[15:0]),
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.CLKB(clk_b),
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.RSTB(rst_b),
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.ADDRB(addr_b),
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.DIB(di_b[15:0]),
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.ENB(ce_b),
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.WEB(we_b),
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.DOB(do_b[15:0])
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);
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//
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// Block 1
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//
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RAMB4_S16_S16 ramb4_s16_s16_1(
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.CLKA(clk_a),
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.RSTA(rst_a),
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.ADDRA(addr_a),
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.DIA(di_a[31:16]),
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.ENA(ce_a),
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.WEA(we_a),
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.DOA(do_a[31:16]),
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.CLKB(clk_b),
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.RSTB(rst_b),
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.ADDRB(addr_b),
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.DIB(di_b[31:16]),
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.ENB(ce_b),
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.WEB(we_b),
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.DOB(do_b[31:16])
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);
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||
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//
|
||
|
|
// Block 2
|
||
|
|
//
|
||
|
|
// block ram2 wires - non generic width of block rams
|
||
|
|
wire [15:0] blk2_di_a = {8'h00, di_a[39:32]} ;
|
||
|
|
wire [15:0] blk2_di_b = {8'h00, di_b[39:32]} ;
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||
|
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||
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wire [15:0] blk2_do_a ;
|
||
|
|
wire [15:0] blk2_do_b ;
|
||
|
|
|
||
|
|
assign do_a[39:32] = blk2_do_a[7:0] ;
|
||
|
|
assign do_b[39:32] = blk2_do_b[7:0] ;
|
||
|
|
|
||
|
|
RAMB4_S16_S16 ramb4_s16_s16_2(
|
||
|
|
.CLKA(clk_a),
|
||
|
|
.RSTA(rst_a),
|
||
|
|
.ADDRA(addr_a),
|
||
|
|
.DIA(blk2_di_a),
|
||
|
|
.ENA(ce_a),
|
||
|
|
.WEA(we_a),
|
||
|
|
.DOA(blk2_do_a),
|
||
|
|
|
||
|
|
.CLKB(clk_b),
|
||
|
|
.RSTB(rst_b),
|
||
|
|
.ADDRB(addr_b),
|
||
|
|
.DIB(blk2_di_b),
|
||
|
|
.ENB(ce_b),
|
||
|
|
.WEB(we_b),
|
||
|
|
.DOB(blk2_do_b)
|
||
|
|
);
|
||
|
|
|
||
|
|
`endif
|
||
|
|
|
||
|
|
`ifdef PCI_WB_RAM_SELECTED
|
||
|
|
`else
|
||
|
|
//
|
||
|
|
// Generic two-port synchronous RAM model
|
||
|
|
//
|
||
|
|
|
||
|
|
//
|
||
|
|
// Generic RAM's registers and wires
|
||
|
|
//
|
||
|
|
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
|
||
|
|
reg [dw-1:0] do_reg_b; // RAM data output register
|
||
|
|
|
||
|
|
//
|
||
|
|
// Data output drivers
|
||
|
|
//
|
||
|
|
assign do_a = {dw{1'b0}} ;
|
||
|
|
assign do_b = do_reg_b ;
|
||
|
|
|
||
|
|
//
|
||
|
|
// RAM read and write
|
||
|
|
//
|
||
|
|
always @(posedge clk_a)
|
||
|
|
if (ce_a && we_a)
|
||
|
|
mem[addr_a] <= #1 di_a;
|
||
|
|
|
||
|
|
//
|
||
|
|
// RAM read and write
|
||
|
|
//
|
||
|
|
always @(posedge clk_b)
|
||
|
|
if (ce_b)
|
||
|
|
do_reg_b <= #1 mem[addr_b];
|
||
|
|
`endif
|
||
|
|
|
||
|
|
// synopsys translate_off
|
||
|
|
initial
|
||
|
|
begin
|
||
|
|
if (dw !== 40)
|
||
|
|
begin
|
||
|
|
$display("RAM instantiation error! Expected RAM width %d, actual %h!", 40, dw) ;
|
||
|
|
$finish ;
|
||
|
|
end
|
||
|
|
`ifdef XILINX_RAMB4
|
||
|
|
if (aw !== 8)
|
||
|
|
begin
|
||
|
|
$display("RAM instantiation error! Expected RAM address width %d, actual %h!", 40, aw) ;
|
||
|
|
$finish ;
|
||
|
|
end
|
||
|
|
`endif
|
||
|
|
// currenlty only artisan ram of depth 256 is supported - they don't provide generic ram models
|
||
|
|
`ifdef ARTISAN_SDP
|
||
|
|
if (aw !== 8)
|
||
|
|
begin
|
||
|
|
$display("RAM instantiation error! Expected RAM address width %d, actual %h!", 40, aw) ;
|
||
|
|
$finish ;
|
||
|
|
end
|
||
|
|
`endif
|
||
|
|
end
|
||
|
|
// synopsys translate_on
|
||
|
|
|
||
|
|
endmodule
|
||
|
|
|