72 lines
1.8 KiB
Coq
72 lines
1.8 KiB
Coq
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 05/05/2021 10:29:55 AM
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// Design Name:
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// Module Name: configuration_manager
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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`include "clock_divider.v"
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`include "pulse_generator.v"
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module configuration_manager(
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input clk_in,
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output prog_reset,
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output prog_clk,
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output ccff_head,
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output configuration_done
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);
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parameter START_CYCLE=3; // Start configuration on cycle 3 of prog_clk
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parameter CONFIGURATION_CLK_DIV_SIZE=12; // Divide clk_in (50MHz) by 4096 (2^12) times
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wire prog_clk_out; // prog_clk signal from clk_divider
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wire ccff_head_out;
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assign ccff_head = ccff_head_out & ~prog_reset;
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assign prog_clk = prog_clk_out & ~configuration_done; // prog_clk will stop when configuration done
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// PRESET
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// Programming reset will be enabled until START_CYCLE
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reset_generator #(
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.INITIAL_VALUE(1),
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.ACTIVE_CYCLES(START_CYCLE)
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) prog_reset_generator(
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.clk(~prog_clk),
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.pulse(prog_reset)
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);
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// PROG_CLK
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// Divide pl_clk (50MHz) by 4096 (2^12) times
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clock_divider #(
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.CLK_DIVIDER_SIZE(CONFIGURATION_CLK_DIV_SIZE)
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) prog_clk_divider (
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.clk_in(clk_in),
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.clk_out(prog_clk_out)
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);
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// Instantiate bitstream loader
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bitstream_loader loader (
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.prog_clk(prog_clk),
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.config_chain_head(ccff_head_out),
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.start(~prog_reset),
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.done(configuration_done)
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);
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endmodule
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