245 lines
7.8 KiB
Coq
245 lines
7.8 KiB
Coq
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE Memory Controller ////
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//// Data Path Module ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// www.asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: mc_dp.v,v 1.6 2002/01/21 13:08:52 rudi Exp $
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//
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// $Date: 2002/01/21 13:08:52 $
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// $Revision: 1.6 $
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// $Author: rudi $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: mc_dp.v,v $
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// Revision 1.6 2002/01/21 13:08:52 rudi
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//
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// Fixed several minor bugs, cleaned up the code further ...
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//
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// Revision 1.5 2001/12/11 02:47:19 rudi
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//
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// - Made some changes not to expect clock during reset ...
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//
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// Revision 1.4 2001/11/29 02:16:28 rudi
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//
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//
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// - More Synthesis cleanup, mostly for speed
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// - Several bug fixes
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// - Changed code to avoid auto-precharge and
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// burst-terminate combinations (apparently illegal ?)
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// Now we will do a manual precharge ...
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//
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// Revision 1.3 2001/09/24 00:38:21 rudi
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//
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// Changed Reset to be active high and async.
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//
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// Revision 1.2 2001/08/10 08:16:21 rudi
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//
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// - Changed IO names to be more clear.
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// - Uniquifyed define names to be core specific.
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// - Removed "Refresh Early" configuration
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//
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// Revision 1.1 2001/07/29 07:34:41 rudi
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//
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//
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// 1) Changed Directory Structure
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// 2) Fixed several minor bugs
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//
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// Revision 1.2 2001/06/03 11:37:17 rudi
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//
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//
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// 1) Fixed Chip Select Mask Register
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// - Power On Value is now all ones
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// - Comparison Logic is now correct
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//
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// 2) All resets are now asynchronous
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//
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// 3) Converted Power On Delay to an configurable item
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//
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// 4) Added reset to Chip Select Output Registers
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//
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// 5) Forcing all outputs to Hi-Z state during reset
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//
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// Revision 1.1.1.1 2001/05/13 09:39:47 rudi
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// Created Directory Structure
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//
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//
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//
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//
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`include "mc_defines.v"
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module mc_dp( clk, rst, csc,
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wb_cyc_i, wb_stb_i, wb_ack_o, mem_ack, wb_data_i, wb_data_o,
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wb_read_go, wb_we_i,
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mc_clk, mc_data_del, mc_dp_i, mc_data_o, mc_dp_o,
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dv, pack_le0, pack_le1, pack_le2,
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byte_en, par_err
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);
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input clk, rst;
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input [31:0] csc;
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input wb_cyc_i;
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input wb_stb_i;
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input mem_ack;
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input wb_ack_o;
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input [31:0] wb_data_i;
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output [31:0] wb_data_o;
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input wb_read_go;
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input wb_we_i;
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input mc_clk;
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input [35:0] mc_data_del;
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input [3:0] mc_dp_i;
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output [31:0] mc_data_o;
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output [3:0] mc_dp_o;
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input dv;
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input pack_le0, pack_le1, pack_le2; // Pack Latch Enable
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input [3:0] byte_en; // High Active byte enables
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output par_err;
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////////////////////////////////////////////////////////////////////
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//
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// Local Registers & Wires
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//
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reg [31:0] wb_data_o;
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reg [31:0] mc_data_o;
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wire [35:0] rd_fifo_out;
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wire rd_fifo_clr;
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reg [3:0] mc_dp_o;
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reg par_err_r;
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reg [7:0] byte0, byte1, byte2;
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reg [31:0] mc_data_d;
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wire [2:0] mem_type;
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wire [1:0] bus_width;
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wire pen;
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wire re;
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// Aliases
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assign mem_type = csc[3:1];
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assign bus_width = csc[5:4];
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assign pen = csc[11];
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////////////////////////////////////////////////////////////////////
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//
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// WB READ Data Path
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//
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always @(mem_type or rd_fifo_out or mc_data_d)
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if( (mem_type == `MC_MEM_TYPE_SDRAM) |
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(mem_type == `MC_MEM_TYPE_SRAM) ) wb_data_o = rd_fifo_out[31:0];
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else wb_data_o = mc_data_d;
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//assign rd_fifo_clr = !(rst | !wb_cyc_i | (wb_we_i & wb_stb_i) );
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assign rd_fifo_clr = !wb_cyc_i | (wb_we_i & wb_stb_i);
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assign re = wb_ack_o & wb_read_go;
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mc_rd_fifo u0(
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.clk( clk ),
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.rst( rst ),
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.clr( rd_fifo_clr ),
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.din( mc_data_del ),
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.we( dv ),
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.dout( rd_fifo_out ),
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.re( re )
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);
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////////////////////////////////////////////////////////////////////
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//
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// WB WRITE Data Path
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//
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always @(posedge clk)
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if(wb_ack_o | (mem_type != `MC_MEM_TYPE_SDRAM) )
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mc_data_o <= #1 wb_data_i;
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////////////////////////////////////////////////////////////////////
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//
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// Read Data Packing
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//
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always @(posedge clk)
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if(pack_le0) byte0 <= #1 mc_data_del[7:0];
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always @(posedge clk)
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if(pack_le1 & (bus_width == `MC_BW_8)) byte1 <= #1 mc_data_del[7:0];
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else
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if(pack_le0 & (bus_width == `MC_BW_16)) byte1 <= #1 mc_data_del[15:8];
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always @(posedge clk)
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if(pack_le2) byte2 <= #1 mc_data_del[7:0];
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always @(bus_width or mc_data_del or byte0 or byte1 or byte2)
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if(bus_width == `MC_BW_8) mc_data_d = {mc_data_del[7:0], byte2, byte1, byte0};
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else
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if(bus_width == `MC_BW_16) mc_data_d = {mc_data_del[15:0], byte1, byte0};
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else mc_data_d = mc_data_del[31:0];
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////////////////////////////////////////////////////////////////////
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//
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// Parity Generation
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//
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always @(posedge clk)
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if(wb_ack_o | (mem_type != `MC_MEM_TYPE_SDRAM) )
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mc_dp_o <= #1 { ^wb_data_i[31:24], ^wb_data_i[23:16],
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^wb_data_i[15:08], ^wb_data_i[07:00] };
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////////////////////////////////////////////////////////////////////
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//
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// Parity Checking
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//
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assign par_err = !wb_we_i & mem_ack & pen & (
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(( ^rd_fifo_out[31:24] ^ rd_fifo_out[35] ) & byte_en[3] ) |
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(( ^rd_fifo_out[23:16] ^ rd_fifo_out[34] ) & byte_en[2] ) |
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(( ^rd_fifo_out[15:08] ^ rd_fifo_out[33] ) & byte_en[1] ) |
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(( ^rd_fifo_out[07:00] ^ rd_fifo_out[32] ) & byte_en[0] )
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);
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endmodule
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