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OpenFPGA/.travis/openfpga_vpr8_reg_test.sh

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add missing files for Travis
2019-04-10 02:24:37 -05:00
#!/bin/bash
set -e
Added travis fold for Python Task [ci skip]
2019-08-31 23:36:18 -05:00
start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
remove simulation settings from openfpga arch XML update travis to split CI tests fix errors in travis configuration fixing travis errors in scripts keep fixing travis fix travis on build.sh bug fixing in travis CI bug fix in travis regression test run fixing bugs in the travis scripts bug fix in travis script: remove common.sh in regression test call keep bug fixing in travis
2020-06-11 13:05:12 -05:00
cd ${TRAVIS_BUILD_DIR}
add duplicate_grid_pin to travis integration
2019-12-30 15:06:20 -06:00
deploy openfpga shell in Travis CI
2020-04-12 13:57:13 -05:00
###############################################
# OpenFPGA Shell with VPR8
# (Will replace all the old tests)
##############################################
echo -e "Testing OpenFPGA Shell";
fixed a bug in single mode FPGA; add arch to regression test; deploy full testbench verification on Travis CI
2020-04-15 16:48:33 -05:00
echo -e "Testing configuration chain of a K4N4 FPGA";
file moving in regression tests
2020-05-29 16:59:57 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/configuration_chain --debug --show_thread_logs
deploy the preconfig testbench cases to CI
2020-05-29 17:14:22 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/preconfig_testbench/configuration_chain --debug --show_thread_logs
fixed a bug in single mode FPGA; add arch to regression test; deploy full testbench verification on Travis CI
2020-04-15 16:48:33 -05:00
deploy frame-based configuration protocol to travis CI
2020-05-29 00:07:03 -05:00
echo -e "Testing fram-based configuration protocol of a K4N4 FPGA";
file moving in regression tests
2020-05-29 16:59:57 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/configuration_frame --debug --show_thread_logs
deploy fast configuration testcase to CI
2020-05-29 19:23:12 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/fast_configuration_frame --debug --show_thread_logs
deploy the preconfig testbench cases to CI
2020-05-29 17:14:22 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/preconfig_testbench/configuration_frame --debug --show_thread_logs
deploy frame-based configuration protocol to travis CI
2020-05-29 00:07:03 -05:00
deploy memory bank regression tests to CI
2020-05-30 21:58:02 -05:00
echo -e "Testing memory bank configuration protocol of a K4N4 FPGA";
try to deploy the memory bank protocol test case to CI
2020-05-31 17:14:38 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/memory_bank --debug --show_thread_logs
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/fast_memory_bank --debug --show_thread_logs
deploy preconfig regression test for memory bank to CI
2020-05-30 21:59:40 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/preconfig_testbench/memory_bank --debug --show_thread_logs
deploy memory bank regression tests to CI
2020-05-30 21:58:02 -05:00
deploy the flatten configuration memory testcase to CI
2020-05-30 13:23:48 -05:00
echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FPGA";
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/flatten_memory --debug --show_thread_logs
deploy the standalone preconfig testcase to CI
2020-05-30 13:26:05 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/preconfig_testbench/flatten_memory --debug --show_thread_logs
deploy the flatten configuration memory testcase to CI
2020-05-30 13:23:48 -05:00
deploy the tests to CI
2020-05-04 13:36:06 -05:00
echo -e "Testing user-defined simulation settings: clock frequency and number of cycles";
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/fixed_simulation_settings --debug --show_thread_logs
add more test cases about LUT design and deploy to CI
2020-05-01 16:05:59 -05:00
echo -e "Testing Verilog generation for LUTs: a single mode LUT6 FPGA using micro benchmarks";
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/lut_design/single_mode --debug --show_thread_logs
deploy single mode in regression tests
2020-04-20 14:16:52 -05:00
add more test cases about LUT design and deploy to CI
2020-05-01 16:05:59 -05:00
echo -e "Testing Verilog generation for LUTs: simple fracturable LUT6 ";
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/lut_design/frac_lut --debug --show_thread_logs
echo -e "Testing Verilog generation for LUTs: LUT6 with intermediate buffers";
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/lut_design/intermediate_buffer --debug --show_thread_logs
deploy openfpga shell in Travis CI
2020-04-12 13:57:13 -05:00
add untileable test case to Travis CI
2020-04-12 15:08:24 -05:00
echo -e "Testing Verilog generation with VPR's untileable routing architecture ";
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/untileable --debug --show_thread_logs
add test case of BRAM to Travis CI
2020-04-12 15:27:05 -05:00
echo -e "Testing Verilog generation with hard adder chain in CLBs ";
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/hard_adder --debug --show_thread_logs
echo -e "Testing Verilog generation with 16k block RAMs ";
reshape bram test case
2020-04-12 15:32:09 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/bram/dpram16k --debug --show_thread_logs
add test case of BRAM to Travis CI
2020-04-12 15:27:05 -05:00
add test case of wide BRAM 16k to Travis CI
2020-04-12 15:37:08 -05:00
echo -e "Testing Verilog generation with 16k block RAMs spanning two columns ";
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/bram/wide_dpram16k --debug --show_thread_logs
add io test cases to Travis CI
2020-04-12 16:01:47 -05:00
echo -e "Testing Verilog generation with different I/O capacities on each side of an FPGA ";
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/io/multi_io_capacity --debug --show_thread_logs
echo -e "Testing Verilog generation with I/Os only on left and right sides of an FPGA ";
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/io/reduced_io --debug --show_thread_logs
add long adder chain to Travis CI
2020-04-12 16:43:19 -05:00
echo -e "Testing Verilog generation with adder chain across an FPGA";
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/fabric_chain/adder_chain --debug --show_thread_logs
add register chain and scan chain to Travis CI
2020-04-12 16:28:22 -05:00
echo -e "Testing Verilog generation with shift register chain across an FPGA";
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/fabric_chain/register_chain --debug --show_thread_logs
echo -e "Testing Verilog generation with scan chain across an FPGA";
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/fabric_chain/scan_chain --debug --show_thread_logs
add test cases on different routing multiplexer circuit designs to Travis CI
2020-04-12 16:39:45 -05:00
echo -e "Testing Verilog generation with routing mutliplexers implemented by tree structure";
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/mux_design/tree_structure --debug --show_thread_logs
echo -e "Testing Verilog generation with routing mutliplexers implemented by standard cell MUX2";
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/mux_design/stdcell_mux2 --debug --show_thread_logs
deploy local encoder to CI
2020-05-01 15:56:07 -05:00
echo -e "Testing Verilog generation with routing mutliplexers implemented by local encoders";
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/mux_design/local_encoder --debug --show_thread_logs
add behavioral verilog test case to Travis CI
2020-04-12 20:55:47 -05:00
echo -e "Testing Verilog generation with behavioral description";
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/behavioral_verilog --debug --show_thread_logs
add implicit verilog test case to Travis CI
2020-04-12 21:00:20 -05:00
echo -e "Testing implicit Verilog generation";
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/implicit_verilog --debug --show_thread_logs
add flatten routing test case to Travis CI
2020-04-12 21:06:40 -05:00
echo -e "Testing Verilog generation with flatten routing modules";
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/flatten_routing --debug --show_thread_logs
add duplicated_grid_pin test case to Travis CI
2020-04-12 21:10:51 -05:00
echo -e "Testing Verilog generation with duplicated grid output pins";
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/duplicated_grid_pin --debug --show_thread_logs
add spypad to regression test
2020-04-22 15:42:30 -05:00
echo -e "Testing Verilog generation with spy output pads";
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/spypad --debug --show_thread_logs
deploy the fabric/testbench generation only cases to travis
2020-04-28 19:24:20 -05:00
echo -e "Testing fabric Verilog generation only";
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/generate_fabric --debug --show_thread_logs
echo -e "Testing Verilog testbench generation only";
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/generate_testbench --debug --show_thread_logs
add time unit test for SDC generation to CI
2020-05-05 13:43:49 -05:00
echo -e "Testing SDC generation with time units";
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/sdc_time_unit --debug --show_thread_logs
deploy fabric key test cases to CI
2020-06-12 12:38:05 -05:00
echo -e "Testing Secured FPGA fabrics";
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/fabric_key/generate_vanilla_key --debug --show_thread_logs
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/fabric_key/generate_random_key --debug --show_thread_logs
deploy load external key test case to CI
2020-06-12 22:41:21 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/fabric_key/load_external_key --debug --show_thread_logs
deploy fabric key test cases to CI
2020-06-12 12:38:05 -05:00
update travis script with example run on MCNC big20
2020-04-28 19:16:52 -05:00
# Verify MCNC big20 benchmark suite with ModelSim
# Please make sure you have ModelSim installed in the environment
# Otherwise, it will fail
#python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/mcnc_big20 --debug --show_thread_logs --maxthreads 20
#python3 openfpga_flow/scripts/run_modelsim.py openfpga_shell/mcnc_big20 --run_sim
Added travis fold for Python Task [ci skip]
2019-08-31 23:36:18 -05:00
end_section "OpenFPGA.TaskTun"