OpenFPGA/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/sasc.blif

# Benchmark "sasc" written by ABC on Mon Aug 29 15:33:11 2005
.model sasc
.inputs clk rst rxd_i cts_i sio_ce sio_ce_x4 re_i we_i din_i[0] din_i[1] \
 din_i[2] din_i[3] din_i[4] din_i[5] din_i[6] din_i[7]
.outputs txd_o rts_o full_o empty_o dout_o[0] dout_o[1] dout_o[2] dout_o[3] \
 dout_o[4] dout_o[5] dout_o[6] dout_o[7]

.latch rx_fifo_gb_reg_in rx_fifo_gb_reg  2
.latch \rx_fifo_wp_reg[0]_in \rx_fifo_wp_reg[0]  0
.latch \rx_fifo_mem_reg[1][6]_in \rx_fifo_mem_reg[1][6]  2
.latch \rx_fifo_mem_reg[1][7]_in \rx_fifo_mem_reg[1][7]  2
.latch \rx_fifo_mem_reg[2][0]_in \rx_fifo_mem_reg[2][0]  2
.latch \rx_fifo_mem_reg[2][1]_in \rx_fifo_mem_reg[2][1]  2
.latch \rx_fifo_mem_reg[2][2]_in \rx_fifo_mem_reg[2][2]  2
.latch \rx_fifo_mem_reg[2][3]_in \rx_fifo_mem_reg[2][3]  2
.latch \rx_fifo_mem_reg[2][4]_in \rx_fifo_mem_reg[2][4]  2
.latch \rx_fifo_mem_reg[2][5]_in \rx_fifo_mem_reg[2][5]  2
.latch \rx_fifo_mem_reg[2][6]_in \rx_fifo_mem_reg[2][6]  2
.latch \rx_fifo_mem_reg[2][7]_in \rx_fifo_mem_reg[2][7]  2
.latch \rx_fifo_mem_reg[1][0]_in \rx_fifo_mem_reg[1][0]  2
.latch \rx_fifo_mem_reg[1][1]_in \rx_fifo_mem_reg[1][1]  2
.latch \rx_fifo_mem_reg[1][2]_in \rx_fifo_mem_reg[1][2]  2
.latch \rx_fifo_mem_reg[1][3]_in \rx_fifo_mem_reg[1][3]  2
.latch \rx_fifo_mem_reg[1][4]_in \rx_fifo_mem_reg[1][4]  2
.latch \rx_fifo_mem_reg[1][5]_in \rx_fifo_mem_reg[1][5]  2
.latch \rx_fifo_mem_reg[3][0]_in \rx_fifo_mem_reg[3][0]  2
.latch \rx_fifo_mem_reg[3][1]_in \rx_fifo_mem_reg[3][1]  2
.latch \rx_fifo_mem_reg[3][2]_in \rx_fifo_mem_reg[3][2]  2
.latch \rx_fifo_mem_reg[3][3]_in \rx_fifo_mem_reg[3][3]  2
.latch \rx_fifo_mem_reg[3][4]_in \rx_fifo_mem_reg[3][4]  2
.latch \rx_fifo_mem_reg[3][5]_in \rx_fifo_mem_reg[3][5]  2
.latch \rx_fifo_mem_reg[3][6]_in \rx_fifo_mem_reg[3][6]  2
.latch \rx_fifo_mem_reg[3][7]_in \rx_fifo_mem_reg[3][7]  2
.latch \rx_fifo_mem_reg[0][0]_in \rx_fifo_mem_reg[0][0]  2
.latch \rx_fifo_mem_reg[0][1]_in \rx_fifo_mem_reg[0][1]  2
.latch \rx_fifo_mem_reg[0][2]_in \rx_fifo_mem_reg[0][2]  2
.latch \rx_fifo_mem_reg[0][3]_in \rx_fifo_mem_reg[0][3]  2
.latch \rx_fifo_mem_reg[0][4]_in \rx_fifo_mem_reg[0][4]  2
.latch \rx_fifo_mem_reg[0][5]_in \rx_fifo_mem_reg[0][5]  2
.latch \rx_fifo_mem_reg[0][6]_in \rx_fifo_mem_reg[0][6]  2
.latch \rx_fifo_mem_reg[0][7]_in \rx_fifo_mem_reg[0][7]  2
.latch \rx_bit_cnt_reg[1]_in \rx_bit_cnt_reg[1]  2
.latch \rx_fifo_wp_reg[1]_in \rx_fifo_wp_reg[1]  0
.latch \rx_bit_cnt_reg[3]_in \rx_bit_cnt_reg[3]  2
.latch \rx_bit_cnt_reg[0]_in \rx_bit_cnt_reg[0]  2
.latch \rx_bit_cnt_reg[2]_in \rx_bit_cnt_reg[2]  2
.latch \rxr_reg[3]_in \rxr_reg[3]  2
.latch \rxr_reg[9]_in \rxr_reg[9]  2
.latch \rxr_reg[2]_in \rxr_reg[2]  2
.latch \rxr_reg[4]_in \rxr_reg[4]  2
.latch \rxr_reg[5]_in \rxr_reg[5]  2
.latch \rxr_reg[6]_in \rxr_reg[6]  2
.latch \rxr_reg[8]_in \rxr_reg[8]  2
.latch \rxr_reg[7]_in \rxr_reg[7]  2
.latch \tx_bit_cnt_reg[3]_in \tx_bit_cnt_reg[3]  2
.latch tx_fifo_gb_reg_in tx_fifo_gb_reg  2
.latch \hold_reg_reg[6]_in \hold_reg_reg[6]  2
.latch \hold_reg_reg[7]_in \hold_reg_reg[7]  2
.latch \hold_reg_reg[8]_in \hold_reg_reg[8]  2
.latch \hold_reg_reg[1]_in \hold_reg_reg[1]  2
.latch \hold_reg_reg[2]_in \hold_reg_reg[2]  2
.latch \hold_reg_reg[3]_in \hold_reg_reg[3]  2
.latch \hold_reg_reg[4]_in \hold_reg_reg[4]  2
.latch \tx_bit_cnt_reg[2]_in \tx_bit_cnt_reg[2]  2
.latch \hold_reg_reg[5]_in \hold_reg_reg[5]  2
.latch txf_empty_r_reg_in txf_empty_r_reg  2
.latch \tx_fifo_mem_reg[2][1]_in \tx_fifo_mem_reg[2][1]  2
.latch \dpll_state_reg[0]_in \dpll_state_reg[0]  1
.latch rts_o_reg_in  rts_o_reg  2
.latch \tx_bit_cnt_reg[0]_in \tx_bit_cnt_reg[0]  2
.latch \tx_fifo_mem_reg[1][0]_in \tx_fifo_mem_reg[1][0]  2
.latch \tx_fifo_mem_reg[1][1]_in \tx_fifo_mem_reg[1][1]  2
.latch \tx_fifo_mem_reg[1][2]_in \tx_fifo_mem_reg[1][2]  2
.latch \tx_fifo_mem_reg[1][3]_in \tx_fifo_mem_reg[1][3]  2
.latch \tx_fifo_mem_reg[1][4]_in \tx_fifo_mem_reg[1][4]  2
.latch \tx_fifo_mem_reg[1][6]_in \tx_fifo_mem_reg[1][6]  2
.latch \tx_fifo_mem_reg[1][7]_in \tx_fifo_mem_reg[1][7]  2
.latch \tx_fifo_mem_reg[2][0]_in \tx_fifo_mem_reg[2][0]  2
.latch \tx_fifo_mem_reg[2][2]_in \tx_fifo_mem_reg[2][2]  2
.latch \tx_fifo_mem_reg[2][3]_in \tx_fifo_mem_reg[2][3]  2
.latch \tx_fifo_mem_reg[2][4]_in \tx_fifo_mem_reg[2][4]  2
.latch \tx_fifo_mem_reg[2][6]_in \tx_fifo_mem_reg[2][6]  2
.latch \tx_fifo_mem_reg[2][7]_in \tx_fifo_mem_reg[2][7]  2
.latch txd_o_reg_in  txd_o_reg  2
.latch \tx_fifo_rp_reg[1]_in \tx_fifo_rp_reg[1]  0
.latch \hold_reg_reg[0]_in \hold_reg_reg[0]  2
.latch \tx_fifo_mem_reg[1][5]_in \tx_fifo_mem_reg[1][5]  2
.latch \tx_fifo_mem_reg[2][5]_in \tx_fifo_mem_reg[2][5]  2
.latch \tx_fifo_mem_reg[3][1]_in \tx_fifo_mem_reg[3][1]  2
.latch \tx_fifo_mem_reg[3][6]_in \tx_fifo_mem_reg[3][6]  2
.latch rx_valid_r_reg_in rx_valid_r_reg  2
.latch \tx_fifo_mem_reg[3][5]_in \tx_fifo_mem_reg[3][5]  2
.latch change_reg_in change_reg  2
.latch \tx_fifo_mem_reg[0][0]_in \tx_fifo_mem_reg[0][0]  2
.latch \tx_fifo_mem_reg[0][3]_in \tx_fifo_mem_reg[0][3]  2
.latch \tx_fifo_mem_reg[0][4]_in \tx_fifo_mem_reg[0][4]  2
.latch \tx_fifo_mem_reg[0][7]_in \tx_fifo_mem_reg[0][7]  2
.latch \tx_fifo_mem_reg[0][2]_in \tx_fifo_mem_reg[0][2]  2
.latch \tx_fifo_mem_reg[3][0]_in \tx_fifo_mem_reg[3][0]  2
.latch \tx_fifo_mem_reg[3][2]_in \tx_fifo_mem_reg[3][2]  2
.latch \tx_fifo_mem_reg[3][3]_in \tx_fifo_mem_reg[3][3]  2
.latch \tx_fifo_mem_reg[3][4]_in \tx_fifo_mem_reg[3][4]  2
.latch \tx_fifo_mem_reg[3][7]_in \tx_fifo_mem_reg[3][7]  2
.latch \rx_fifo_rp_reg[1]_in \rx_fifo_rp_reg[1]  0
.latch \hold_reg_reg[9]_in \hold_reg_reg[9]  2
.latch \tx_fifo_mem_reg[0][6]_in \tx_fifo_mem_reg[0][6]  2
.latch \tx_fifo_mem_reg[0][5]_in \tx_fifo_mem_reg[0][5]  2
.latch \tx_fifo_mem_reg[0][1]_in \tx_fifo_mem_reg[0][1]  2
.latch \tx_bit_cnt_reg[1]_in \tx_bit_cnt_reg[1]  2
.latch rx_sio_ce_reg_in rx_sio_ce_reg  2
.latch shift_en_r_reg_in shift_en_r_reg  2
.latch \tx_fifo_wp_reg[1]_in \tx_fifo_wp_reg[1]  0
.latch \dpll_state_reg[1]_in \dpll_state_reg[1]  0
.latch rx_valid_reg_in rx_valid_reg  2
.latch \rx_fifo_rp_reg[0]_in \rx_fifo_rp_reg[0]  0
.latch rx_go_reg_in  rx_go_reg  2
.latch \tx_fifo_rp_reg[0]_in \tx_fifo_rp_reg[0]  0
.latch load_reg_in   load_reg  2
.latch rx_sio_ce_r2_reg_in rx_sio_ce_r2_reg  2
.latch \tx_fifo_wp_reg[0]_in \tx_fifo_wp_reg[0]  0
.latch shift_en_reg_in shift_en_reg  2
.latch rx_sio_ce_r1_reg_in rx_sio_ce_r1_reg  2
.latch rxd_r_reg_in  rxd_r_reg  2
.latch rxd_s_reg_in  rxd_s_reg  2

.names [145]
 0
.names [146]
 1
.names rx_fifo_gb_reg [147]
1 1
.names \rx_fifo_wp_reg[0] [148]
1 1
.names \rx_fifo_mem_reg[1][6] [149]
1 1
.names \rx_fifo_mem_reg[1][7] [150]
1 1
.names \rx_fifo_mem_reg[2][0] [151]
1 1
.names \rx_fifo_mem_reg[2][1] [152]
1 1
.names \rx_fifo_mem_reg[2][2] [153]
1 1
.names \rx_fifo_mem_reg[2][3] [154]
1 1
.names \rx_fifo_mem_reg[2][4] [155]
1 1
.names \rx_fifo_mem_reg[2][5] [156]
1 1
.names \rx_fifo_mem_reg[2][6] [157]
1 1
.names \rx_fifo_mem_reg[2][7] [158]
1 1
.names \rx_fifo_mem_reg[1][0] [159]
1 1
.names \rx_fifo_mem_reg[1][1] [160]
1 1
.names \rx_fifo_mem_reg[1][2] [161]
1 1
.names \rx_fifo_mem_reg[1][3] [162]
1 1
.names \rx_fifo_mem_reg[1][4] [163]
1 1
.names \rx_fifo_mem_reg[1][5] [164]
1 1
.names \rx_fifo_mem_reg[3][0] [165]
1 1
.names \rx_fifo_mem_reg[3][1] [166]
1 1
.names \rx_fifo_mem_reg[3][2] [167]
1 1
.names \rx_fifo_mem_reg[3][3] [168]
1 1
.names \rx_fifo_mem_reg[3][4] [169]
1 1
.names \rx_fifo_mem_reg[3][5] [170]
1 1
.names \rx_fifo_mem_reg[3][6] [171]
1 1
.names \rx_fifo_mem_reg[3][7] [172]
1 1
.names \rx_fifo_mem_reg[0][0] [173]
1 1
.names \rx_fifo_mem_reg[0][1] [174]
1 1
.names \rx_fifo_mem_reg[0][2] [175]
1 1
.names \rx_fifo_mem_reg[0][3] [176]
1 1
.names \rx_fifo_mem_reg[0][4] [177]
1 1
.names \rx_fifo_mem_reg[0][5] [178]
1 1
.names \rx_fifo_mem_reg[0][6] [179]
1 1
.names \rx_fifo_mem_reg[0][7] [180]
1 1
.names [230] [607] [648] rx_fifo_gb_reg_in
11- 0
--1 0
.names \rx_bit_cnt_reg[1] [182]
1 1
.names \rx_fifo_wp_reg[1] [183]
1 1
.names \rx_bit_cnt_reg[3] [184]
1 1
.names [672] [625] [232] \rx_fifo_wp_reg[0]_in
00- 1
--0 1
.names [414] [150] [242] \rx_fifo_mem_reg[1][7]_in
01- 1
1-1 1
.names [352] [151] [242] \rx_fifo_mem_reg[2][0]_in
01- 1
1-1 1
.names [353] [152] [245] \rx_fifo_mem_reg[2][1]_in
01- 1
1-1 1
.names [413] [149] [244] \rx_fifo_mem_reg[1][6]_in
01- 1
1-1 1
.names \rx_bit_cnt_reg[0] [190]
1 1
.names \rx_bit_cnt_reg[2] [191]
1 1
.names [355] [154] [243] \rx_fifo_mem_reg[2][3]_in
01- 1
1-1 1
.names [354] [153] [245] \rx_fifo_mem_reg[2][2]_in
01- 1
1-1 1
.names [356] [155] [242] \rx_fifo_mem_reg[2][4]_in
01- 1
1-1 1
.names [357] [156] [243] \rx_fifo_mem_reg[2][5]_in
01- 1
1-1 1
.names [358] [157] [245] \rx_fifo_mem_reg[2][6]_in
01- 1
1-1 1
.names [359] [158] [244] \rx_fifo_mem_reg[2][7]_in
01- 1
1-1 1
.names [417] [160] [242] \rx_fifo_mem_reg[1][1]_in
01- 1
1-1 1
.names [415] [159] [245] \rx_fifo_mem_reg[1][0]_in
01- 1
1-1 1
.names [416] [161] [242] \rx_fifo_mem_reg[1][2]_in
01- 1
1-1 1
.names [418] [162] [243] \rx_fifo_mem_reg[1][3]_in
01- 1
1-1 1
.names [419] [163] [242] \rx_fifo_mem_reg[1][4]_in
01- 1
1-1 1
.names [420] [164] [244] \rx_fifo_mem_reg[1][5]_in
01- 1
1-1 1
.names [360] [165] [244] \rx_fifo_mem_reg[3][0]_in
01- 1
1-1 1
.names [361] [166] [245] \rx_fifo_mem_reg[3][1]_in
01- 1
1-1 1
.names [362] [167] [243] \rx_fifo_mem_reg[3][2]_in
01- 1
1-1 1
.names [363] [168] [244] \rx_fifo_mem_reg[3][3]_in
01- 1
1-1 1
.names [364] [169] [244] \rx_fifo_mem_reg[3][4]_in
01- 1
1-1 1
.names [366] [170] [243] \rx_fifo_mem_reg[3][5]_in
01- 1
1-1 1
.names [367] [171] [245] \rx_fifo_mem_reg[3][6]_in
01- 1
1-1 1
.names [368] [172] [245] \rx_fifo_mem_reg[3][7]_in
01- 1
1-1 1
.names [373] [173] [244] \rx_fifo_mem_reg[0][0]_in
01- 1
1-1 1
.names [369] [174] [243] \rx_fifo_mem_reg[0][1]_in
01- 1
1-1 1
.names [374] [175] [245] \rx_fifo_mem_reg[0][2]_in
01- 1
1-1 1
.names [375] [176] [244] \rx_fifo_mem_reg[0][3]_in
01- 1
1-1 1
.names [378] [177] [242] \rx_fifo_mem_reg[0][4]_in
01- 1
1-1 1
.names [376] [178] [242] \rx_fifo_mem_reg[0][5]_in
01- 1
1-1 1
.names [372] [179] [243] \rx_fifo_mem_reg[0][6]_in
01- 1
1-1 1
.names [377] [180] [243] \rx_fifo_mem_reg[0][7]_in
01- 1
1-1 1
.names \rxr_reg[3] [220]
1 1
.names \rxr_reg[9] [221]
1 1
.names \rxr_reg[2] [222]
1 1
.names \rxr_reg[4] [223]
1 1
.names \rxr_reg[5] [224]
1 1
.names \rxr_reg[6] [225]
1 1
.names \rxr_reg[8] [226]
1 1
.names \rxr_reg[7] [227]
1 1
.names [543] [246] rst \rx_bit_cnt_reg[1]_in
00- 1
--0 1
.names [251] [543] rst \rx_bit_cnt_reg[3]_in
00- 1
--0 1
.names [322] [247] [500] [230]
111 0
.names [253] [467] \rx_bit_cnt_reg[0]_in
00 1
.names [672] [625] [232]
11 0
.names [252] [467] \rx_bit_cnt_reg[2]_in
00 1
.names rxd_r_reg_in [221] [280] \rxr_reg[9]_in
01- 1
1-1 1
.names [220] [222] [280] \rxr_reg[2]_in
01- 1
1-1 1
.names [223] [220] [280] \rxr_reg[3]_in
01- 1
1-1 1
.names [224] [223] [280] \rxr_reg[4]_in
01- 1
1-1 1
.names [225] [224] [280] \rxr_reg[5]_in
01- 1
1-1 1
.names [227] [225] [280] \rxr_reg[6]_in
01- 1
1-1 1
.names [226] [227] [280] \rxr_reg[7]_in
01- 1
1-1 1
.names [221] [226] [280] \rxr_reg[8]_in
01- 1
1-1 1
.names [247] [242]
0 1
.names [248] [243]
0 1
.names [249] [244]
0 1
.names [250] [245]
0 1
.names [575] [270] [182] [280] [246]
11-- 0
--11 0
.names [673] [247]
0 1
.names [673] [248]
0 1
.names [673] [249]
0 1
.names [673] [250]
0 1
.names [184] [280] [267] [251]
11- 0
--1 0
.names [191] [280] [263] [252]
11- 0
--1 0
.names [629] [280] [262] [253]
11- 0
--1 0
.names \tx_bit_cnt_reg[3] [254]
1 1
.names tx_fifo_gb_reg [255]
0 1
.names \hold_reg_reg[6] [256]
0 1
.names \hold_reg_reg[7] [257]
0 1
.names \hold_reg_reg[8] [258]
0 1
.names \hold_reg_reg[1] [259]
0 1
.names \hold_reg_reg[2] [260]
0 1
.names \hold_reg_reg[3] [261]
0 1
.names [629] [280] [262]
00 1
.names [501] [280] [263]
00 1
.names \hold_reg_reg[4] [264]
0 1
.names \tx_bit_cnt_reg[2] [265]
1 1
.names \hold_reg_reg[5] [266]
0 1
.names [453] [280] [267]
00 1
.names txf_empty_r_reg [268]
0 1
.names [329] [598] rst \tx_bit_cnt_reg[3]_in
00- 1
--0 1
.names [280] [270]
0 1
.names [327] [591] \tx_bit_cnt_reg[2]_in
00 1
.names [513] [383] [598] \hold_reg_reg[6]_in
01- 1
1-1 1
.names [511] [382] [598] \hold_reg_reg[5]_in
01- 1
1-1 1
.names [514] [384] [598] \hold_reg_reg[7]_in
01- 1
1-1 1
.names [516] [385] [598] \hold_reg_reg[8]_in
01- 1
1-1 1
.names [521] [386] [598] \hold_reg_reg[1]_in
01- 1
1-1 1
.names [517] [387] [632] \hold_reg_reg[2]_in
01- 1
1-1 1
.names [515] [388] [632] \hold_reg_reg[3]_in
01- 1
1-1 1
.names [533] [389] [632] \hold_reg_reg[4]_in
01- 1
1-1 1
.names [433] [328] [280]
11 0
.names [572] [371] [648] tx_fifo_gb_reg_in
11- 0
--1 0
.names \tx_fifo_mem_reg[2][1] [282]
1 1
.names \dpll_state_reg[0] [283]
1 1
.names rts_o_reg rts_o
1 1
.names \tx_bit_cnt_reg[0] [285]
1 1
.names \tx_fifo_mem_reg[1][0] [286]
1 1
.names \tx_fifo_mem_reg[1][1] [287]
1 1
.names \tx_fifo_mem_reg[1][2] [288]
1 1
.names \tx_fifo_mem_reg[1][3] [289]
1 1
.names \tx_fifo_mem_reg[1][4] [290]
1 1
.names \tx_fifo_mem_reg[1][6] [291]
1 1
.names \tx_fifo_mem_reg[1][7] [292]
1 1
.names \tx_fifo_mem_reg[2][0] [293]
1 1
.names \tx_fifo_mem_reg[2][2] [294]
1 1
.names \tx_fifo_mem_reg[2][3] [295]
1 1
.names \tx_fifo_mem_reg[2][4] [296]
1 1
.names \tx_fifo_mem_reg[2][6] [297]
1 1
.names \tx_fifo_mem_reg[2][7] [298]
1 1
.names txd_o_reg txd_o
1 1
.names \tx_fifo_rp_reg[1] [300]
1 1
.names \hold_reg_reg[0] [301]
1 1
.names \tx_fifo_mem_reg[1][5] [302]
1 1
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0 1
.names sio_ce [639]
0 1
.names [261] [640]
0 1
.names [264] [641]
0 1
.names [260] [642]
0 1
.names [190] [643]
0 1
.names [191] [644]
0 1
.names [147] [645]
0 1
.names [256] [646]
0 1
.names sio_ce_x4 [647]
0 1
.names rst [648]
0 1
.names [258] [649]
0 1
.names [454] [650]
0 1
.names [148] [651]
0 1
.names [283] [652]
0 1
.names [255] [653]
0 1
.names [510] [654]
0 1
.names [268] [655]
0 1
.names [265] [656]
0 1
.names [659] [658] [657]
00 1
.names [676] [658]
0 1
.names [660] [666] [659]
11 0
.names [683] [665] [660]
11 0
.names [662] [630] [661]
11 0
.names [663] [662]
0 1
.names [406] [663]
0 1
.names [506] [664]
0 1
.names [320] [665]
0 1
.names [684] [320] [666]
11 0
.names [681] [320] [147] [667]
111 0
.names [669] [686] [147] [668]
111 0
.names [320] [669]
0 1
.names [671] [683] [672] \rx_fifo_wp_reg[1]_in
01- 1
1-1 1
.names [679] [566] [671]
11 0
.names [678] [677] [672]
11 0
.names [674] [677] [673]
11 0
.names [675] [676] [674]
11 0
.names [668] [667] [675]
11 0
.names [606] [623] [676]
11 0
.names [307] rx_valid_r_reg_in [677]
11 1
.names [674] [678]
1 1
.names [682] [680] [679]
11 0
.names [148] [680]
0 1
.names [686] [681]
0 1
.names [685] [682]
0 1
.names [684] [683]
0 1
.names [685] [684]
1 1
.names [686] [685]
1 1
.names [183] [686]
0 1
.names [688] [687]
0 1
.names [300] [688]
0 1
.names [690] [689]
0 1
.names [503] [690]
0 1
.names [692] [691]
0 1
.names [693] [692]
1 1
.names [432] [693]
0 1
.names [584] [694]
0 1
.names [609] [695]
1 1
.names rxd_i rxd_s_reg_in
1 1
.end