41 lines
3.1 KiB
Plaintext
41 lines
3.1 KiB
Plaintext
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#VPR compatible SDC file for benchmark 'mes_noc'
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#*******************************
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# set_time_format
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#*******************************
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# Unsuported by VPR
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#*******************************
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# create_clock
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#*******************************
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create_clock -period 1.0 -name virtual_io_clock
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create_clock -period 1.0 clk
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create_clock -period 1.0 {pll_noc_type0:\using_pll:separate_clk:noc_pll_0|altpll:altpll_component|pll_noc_type0_altpll:auto_generated|wire_pll1_clk[0]}
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create_clock -period 1.0 {pll_noc_type1:\using_pll:use_noc_pll_1:noc_pll_1|altpll:altpll_component|pll_noc_type1_altpll:auto_generated|wire_pll1_clk[0]}
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create_clock -period 1.0 {pll_noc_type2:\using_pll:use_noc_pll_2:noc_pll_2|altpll:altpll_component|pll_noc_type2_altpll:auto_generated|wire_pll1_clk[0]}
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create_clock -period 1.0 {pll_noc_type5:\using_pll:use_noc_pll_5:noc_pll_5|altpll:altpll_component|pll_noc_type5_altpll:auto_generated|wire_pll1_clk[0]}
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create_clock -period 1.0 {pll_noc_type4:\using_pll:use_noc_pll_4:noc_pll_4|altpll:altpll_component|pll_noc_type4_altpll:auto_generated|wire_pll1_clk[0]}
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create_clock -period 1.0 {pll_noc_type3:\using_pll:use_noc_pll_3:noc_pll_3|altpll:altpll_component|pll_noc_type3_altpll:auto_generated|wire_pll1_clk[0]}
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create_clock -period 1.0 {pll_noc_type6:\using_pll:use_noc_pll_6:noc_pll_6|altpll:altpll_component|pll_noc_type6_altpll:auto_generated|wire_pll1_clk[0]}
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create_clock -period 1.0 {pll_noc_type7:\using_pll:use_noc_pll_7:noc_pll_7|altpll:altpll_component|pll_noc_type7_altpll:auto_generated|wire_pll1_clk[0]}
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#*******************************
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# set_clock_uncertainty
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#*******************************
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# Unsupported by VPR. VPR does not model clock uncertainty.
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#*******************************
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# set_input_delay
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#*******************************
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set_input_delay -clock virtual_io_clock -max 0.0 [get_ports *]
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#*******************************
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# set_output_delay
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#*******************************
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set_output_delay -clock virtual_io_clock -max 0.0 [get_ports *]
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#*******************************
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# set_clock_groups
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#*******************************
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set_clock_groups -exclusive -group { clk } -group { pll_noc_type0:\using_pll:separate_clk:noc_pll_0|altpll:altpll_component|pll_noc_type0_altpll:auto_generated|wire_pll1_clk[0] } -group { pll_noc_type1:\using_pll:use_noc_pll_1:noc_pll_1|altpll:altpll_component|pll_noc_type1_altpll:auto_generated|wire_pll1_clk[0] } -group { pll_noc_type2:\using_pll:use_noc_pll_2:noc_pll_2|altpll:altpll_component|pll_noc_type2_altpll:auto_generated|wire_pll1_clk[0] } -group { pll_noc_type5:\using_pll:use_noc_pll_5:noc_pll_5|altpll:altpll_component|pll_noc_type5_altpll:auto_generated|wire_pll1_clk[0] } -group { pll_noc_type4:\using_pll:use_noc_pll_4:noc_pll_4|altpll:altpll_component|pll_noc_type4_altpll:auto_generated|wire_pll1_clk[0] } -group { pll_noc_type3:\using_pll:use_noc_pll_3:noc_pll_3|altpll:altpll_component|pll_noc_type3_altpll:auto_generated|wire_pll1_clk[0] } -group { pll_noc_type6:\using_pll:use_noc_pll_6:noc_pll_6|altpll:altpll_component|pll_noc_type6_altpll:auto_generated|wire_pll1_clk[0] } -group { pll_noc_type7:\using_pll:use_noc_pll_7:noc_pll_7|altpll:altpll_component|pll_noc_type7_altpll:auto_generated|wire_pll1_clk[0] }
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