39 lines
1.6 KiB
C++
39 lines
1.6 KiB
C++
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/********************************************************************
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* This file includes functions to compress the hierachy of routing architecture
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*******************************************************************/
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/* Headers from vtrutil library */
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#include "vtr_time.h"
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#include "vtr_log.h"
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#include "verilog_api.h"
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#include "openfpga_verilog.h"
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/* Include global variables of VPR */
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#include "globals.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* A wrapper function to call the fabric_verilog function of FPGA-Verilog
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*******************************************************************/
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void write_fabric_verilog(OpenfpgaContext& openfpga_ctx,
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const Command& cmd, const CommandContext& cmd_context) {
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CommandOptionId opt_output_dir = cmd.option("file");
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CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
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CommandOptionId opt_verbose = cmd.option("verbose");
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fpga_fabric_verilog(openfpga_ctx.module_graph(),
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openfpga_ctx.arch().circuit_lib,
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openfpga_ctx.mux_lib(),
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g_vpr_ctx.device().grid,
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openfpga_ctx.device_rr_gsb(),
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cmd_context.option_value(cmd, opt_output_dir),
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openfpga_ctx.flow_manager().compress_routing(),
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cmd_context.option_enable(cmd, opt_explicit_port_mapping),
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cmd_context.option_enable(cmd, opt_verbose));
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}
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} /* end namespace openfpga */
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