28 lines
1.4 KiB
ReStructuredText
28 lines
1.4 KiB
ReStructuredText
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.. _file_formats_bitstream_setting:
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Bitstream Setting (.xml)
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------------------------
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An example of bitstream settings is shown as follows.
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This can define a hard-coded bitstream for a reconfigurable resource in FPGA fabrics.
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.. code-block:: xml
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<openfpga_bitstream_setting>
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<pb_type name="<string>" source="eblif" content=".param LUT"/>
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</openfpga_bitstream_setting>
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.. option:: pb_type="<string>"
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The ``pb_type`` name to be constrained, which should be the full path of a ``pb_type`` consistent with VPR's architecture description. For example, ``pb_type="clb.fle[arithmetic].soft_adder.adder_lut4"``
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.. option:: source="<string>"
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The source of the ``pb_type`` bitstream, which could be from a ``.eblif`` file. For example, ``source="eblif"``.
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.. option:: content="<string>"
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The content of the ``pb_type`` bitstream, which could be a keyword in a ``.eblif`` file. For example, ``content=".attr LUT"`` means that the bitstream will be extracted from the ``.attr LUT`` line which is defined under the ``.blif model`` (that is defined under the ``pb_type`` in VPR architecture file).
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.. warning:: Bitstream is a feature for power-users. It may cause wrong bitstream to be generated. For example, the hard-coded bitstream is not compatible with LUTs whose nets may be swapped during routing stage (cause a change on the truth table as well as bitstream). It is users's responsibility to ensure correct bitstream.
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