34 lines
1.0 KiB
Markdown
34 lines
1.0 KiB
Markdown
|
---
|
||
|
name: Pull request
|
||
|
about: Push a change to this project
|
||
|
---
|
||
|
|
||
|
### Motivate of the pull request
|
||
|
- [ ] To address an existing issue. If so, please provide a link to the issue.
|
||
|
- [ ] Breaking new feature. If so, please decribe details in the description part.
|
||
|
|
||
|
### Describe the technical details
|
||
|
- What is currently done? (Provide issue link if applicable)
|
||
|
- What does this pull request change?
|
||
|
|
||
|
### Which part of the code base require a change
|
||
|
**In general, modification on existing submodules are not acceptable. You should push changes to upstream.**
|
||
|
- [ ] VPR
|
||
|
- [ ] OpenFPGA libraries
|
||
|
- [ ] FPGA-Verilog
|
||
|
- [ ] FPGA-Bitstream
|
||
|
- [ ] FPGA-SDC
|
||
|
- [ ] FPGA-SPICE
|
||
|
- [ ] Flow scripts
|
||
|
- [ ] Architecture library
|
||
|
- [ ] Cell library
|
||
|
|
||
|
### Checklist of the pull request
|
||
|
- [ ] Require code changes.
|
||
|
- [ ] Require new tests to be added
|
||
|
- [ ] Require an update on documentation
|
||
|
|
||
|
### Impact of the pull request
|
||
|
- [ ] Require a change on Quality of Results (QoR)
|
||
|
- [ ] Break back-compatibility. If so, please list who may be influenced.
|