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OpenFPGA/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys

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Added fpga_flow script - Working Yosys
2019-08-09 17:49:05 -05:00
# Yosys synthesis script for ${TOP_MODULE}
# Read verilog files
Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
2022-01-17 02:21:29 -06:00
read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES}
Added fpga_flow script - Working Yosys
2019-08-09 17:49:05 -05:00
# Technology mapping
hierarchy -top ${TOP_MODULE}
proc
techmap -D NO_LUT -map +/adff2dff.v
# Synthesis
[Flow] Enable flatten for dff-related yosys scripts
2021-10-30 17:12:34 -05:00
flatten
[Flow] Flatten the synthesis recipe in default yosys script to disable the mapping on DFFE and SDFF
2021-10-30 16:46:12 -05:00
opt_expr
opt_clean
check
opt -nodffe -nosdff
fsm
opt -nodffe -nosdff
wreduce
peepopt
opt_clean
opt -nodffe -nosdff
memory -nomap
opt_clean
opt -fast -full -nodffe -nosdff
memory_map
opt -full -nodffe -nosdff
techmap
opt -fast -nodffe -nosdff
Added fpga_flow script - Working Yosys
2019-08-09 17:49:05 -05:00
clean
# LUT mapping
abc -lut ${LUT_SIZE}
# Check
synth -run check
# Clean and output blif
opt_clean -purge
write_blif ${OUTPUT_BLIF}