107 lines
2.6 KiB
Bash
107 lines
2.6 KiB
Bash
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log_pass()
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{
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printf "%-15s %s %s %s\n" "$1" "$2" "`printf "%20s" "$2" | tr -d a-zA-Z0-9_ | tr ' ' .`" "pass."
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}
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log_fail()
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{
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printf "%-15s %s %s %s\n" "$1" "$2" "`printf "%20s" "$2" | tr -d a-zA-Z0-9_ | tr ' ' .`" "FAIL."
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}
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test_autotest()
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{
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# Usage:
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# test_autotest <test_name> <synth_script> <mod_name> <vlog_file>
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test_name="$1"
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synth_cmd="$2"
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mod_name="$3"
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vlog_file="$4"
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mkdir -p log_test_$test_name
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rm -rf log_test_$test_name/$mod_name.*
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../../yosys -q -l log_test_$test_name/$mod_name.out -o log_test_$test_name/$mod_name.v -p "$synth_cmd" "$vlog_file"
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cat spec/${mod_name}_spec.v scripts/check.v >> log_test_$test_name/$mod_name.v
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iverilog -o log_test_$test_name/$mod_name.bin -D"REFDAT_FN=\"refdat/${mod_name}_refdat.txt\"" log_test_$test_name/$mod_name.v
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if log_test_$test_name/$mod_name.bin 2>&1 | tee -a log_test_$test_name/$mod_name.out | grep -q '++OK++'; then
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mv log_test_$test_name/$mod_name.out log_test_$test_name/$mod_name.txt
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log_pass test_$test_name $mod_name
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else
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mv log_test_$test_name/$mod_name.out log_test_$test_name/$mod_name.err
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log_fail test_$test_name $mod_name
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exit 1
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fi
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}
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test_equiv()
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{
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# Usage:
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# test_equiv <test_name> <synth_script> <sat_options> <mod_name> <vlog_file>
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mkdir -p log_test_$1
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rm -f log_test_$1/$4.txt
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rm -f log_test_$1/$4.err
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if ! ../../yosys -q -l log_test_$1/$4.out - 2> /dev/null <<- EOT
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read_verilog $5
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proc;;
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copy $4 gold
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rename $4 work
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cd work
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$2
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cd ..
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miter -equiv -ignore_gold_x -make_outputs -make_outcmp gold work miter
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flatten miter
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sat $3 -verify -prove trigger 0 -show-inputs -show-outputs miter
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EOT
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then
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log_fail test_$1 $4
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mv log_test_$1/$4.out log_test_$1/$4.err
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exit 1
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fi
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log_pass test_$1 $4
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mv log_test_$1/$4.out log_test_$1/$4.txt
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}
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test_febe()
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{
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# Usage:
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# test_febe <test_name> <synth_script> <extension> <backend> <frontend> <sat_options> <mod_name> <vlog_file>
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# $1 $2 $3 $4 $5 $6 $7 $8
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mkdir -p log_test_$1
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rm -f log_test_$1/$7.txt
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rm -f log_test_$1/$7.err
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if ! ../../yosys -q -l log_test_$1/$7.out - 2> /dev/null <<- EOT
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echo on
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read_verilog $8
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$2
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design -save gold
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dump
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$4 log_test_$1/$7$3
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design -reset
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$5 log_test_$1/$7$3
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design -copy-from gold -as gold $7
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rename $7 gate
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miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter
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sat $6 -verify -prove trigger 0 -show-inputs -show-outputs miter
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EOT
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then
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log_fail test_$1 $7
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mv log_test_$1/$7.out log_test_$1/$7.err
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exit 1
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fi
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log_pass test_$1 $7
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mv log_test_$1/$7.out log_test_$1/$7.txt
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}
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