1208 lines
68 KiB
XML
1208 lines
68 KiB
XML
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<!--
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Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
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- 40 nm technology
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- General purpose logic block:
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K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with all 5 inputs shared)
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with optionally registered outputs
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- Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.
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Height = 6, found on every (8n+2)th column
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- Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.
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Height = 4, found on every (8n+6)th column
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- Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
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Details on Modelling:
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The electrical design of the architecture described here is NOT from an
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optimized, SPICED architecture. Instead, we attempt to create a reasonable
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architecture file by using an existing commercial FPGA to approximate the area,
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delay, and power of the underlying components. This is combined with a reasonable 40 nm
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model of wiring and circuit design for low-level routing components, where available.
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The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also
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has wiring electrical parameters that allow the wire lengths and switch patterns to be
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modified and you will still get reasonable delay results for the new architecture.
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The following describes, in detail, how we obtained the various electrical values for this
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architecture.
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Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar
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architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture.
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(n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)
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This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to
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match the overall target (a 40 nm FPGA).
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We obtain delay numbers by measuring delays of routing, soft logic blocks,
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memories, and multipliers from test circuits on a Stratix IV GX device
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(EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4
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wires. Rmetal and Cmetal values for the routing wires were obtained from work done by Charles
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Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and
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take the R and C data from the ITRS roadmap.
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For the general purpose logic block, we assume that the area and delays of the Stratix IV
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crossbar is close enough to the crossbar modelled here. We use 33 inputs and 20 feedback lines in
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the cluster and a full crossbar, leading to 53:1 multiplexers in front of each BLE input.
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Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to
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36:1 multiplexers. We require 60 such multiplexers, while Stratix IV requires 88 for its more
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complex fracturable BLEs + the extra control signals. We justify this rough approximation as follows:
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The Stratix IV crossbar has more inputs (72 vs. 53) and
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outputs (88 vs. 60) than our full crossbar which should increase its area and delay, but the
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Stratix IV crossbar is also 50% sparse (each mux is 36:1 instead of 53:1) which should reduce its
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area and delay. The total number of crossbar switch points is very similar between the two
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architectures (3160 for SIV and 3180 for the academic architecture below), so we can use the area
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& delay of the Stratix IV crossbar as a good approximation of our crossbar.
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For LUTs, we include LUT
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delays measured from Stratix IV which is dependant on the input used (ie. some
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LUT inputs are faster than others). The CAD tools at the time of VTR 7 does
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not consider differences in LUT input delays.
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Logic block area numbers obtained by scaling overall tile area of a 65nm
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Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out
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routing area at a channel width of 300. We use a channel width of 300 because it can route
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all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
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total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
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choosing a width that provides high routability. The architecture can be routed at different channel
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widths, but we estimate the tile size and hence the physical length of routing wires assuming
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a channel width of 300.
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Sanity checks employed:
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1. We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches
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common electrical design.
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Authors: Jason Luu, Jeff Goeders, Vaughn Betz
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-->
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<architecture>
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<!--
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ODIN II specific config begins
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Describes the types of user-specified netlist blocks (in blif, this corresponds to
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".model [type_of_block]") that this architecture supports.
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Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
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already special structures in blif (.names, .input, .output, and .latch)
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that describe them.
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-->
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<models>
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<model name="multiply">
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<input_ports>
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<port name="a" combinational_sink_ports="out"/>
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<port name="b" combinational_sink_ports="out"/>
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</input_ports>
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<output_ports>
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<port name="out"/>
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</output_ports>
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</model>
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<model name="single_port_ram">
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<input_ports>
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<port name="we" clock="clk"/>
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<!-- control -->
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<port name="addr" clock="clk"/>
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<!-- address lines -->
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<port name="data" clock="clk"/>
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<!-- data lines can be broken down into smaller bit widths minimum size 1 -->
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<port name="clk" is_clock="1"/>
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<!-- memories are often clocked -->
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</input_ports>
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<output_ports>
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<port name="out" clock="clk"/>
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<!-- output can be broken down into smaller bit widths minimum size 1 -->
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</output_ports>
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</model>
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<model name="dual_port_ram">
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<input_ports>
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<port name="we1" clock="clk"/>
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<!-- write enable -->
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<port name="we2" clock="clk"/>
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<!-- write enable -->
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<port name="addr1" clock="clk"/>
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<!-- address lines -->
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<port name="addr2" clock="clk"/>
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<!-- address lines -->
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<port name="data1" clock="clk"/>
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<!-- data lines can be broken down into smaller bit widths minimum size 1 -->
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<port name="data2" clock="clk"/>
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<!-- data lines can be broken down into smaller bit widths minimum size 1 -->
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<port name="clk" is_clock="1"/>
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<!-- memories are often clocked -->
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</input_ports>
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<output_ports>
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<port name="out1" clock="clk"/>
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<!-- output can be broken down into smaller bit widths minimum size 1 -->
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<port name="out2" clock="clk"/>
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<!-- output can be broken down into smaller bit widths minimum size 1 -->
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</output_ports>
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</model>
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</models>
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<tiles>
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<tile name="io" capacity="8">
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<equivalent_sites>
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<site pb_type="io"/>
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</equivalent_sites>
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<input name="outpad" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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<clock name="clock" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
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<pinlocations pattern="custom">
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<loc side="left">io.outpad io.inpad io.clock</loc>
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<loc side="top">io.outpad io.inpad io.clock</loc>
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<loc side="right">io.outpad io.inpad io.clock</loc>
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<loc side="bottom">io.outpad io.inpad io.clock</loc>
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</pinlocations>
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</tile>
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<tile name="clb">
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<equivalent_sites>
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<site pb_type="clb"/>
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</equivalent_sites>
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<input name="I" num_pins="33" equivalent="full"/>
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<output name="O" num_pins="20" equivalent="none"/>
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<clock name="clk" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
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<pinlocations pattern="spread"/>
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</tile>
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<tile name="mult_36" height="4">
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<equivalent_sites>
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<site pb_type="mult_36"/>
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</equivalent_sites>
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<input name="a" num_pins="36"/>
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<input name="b" num_pins="36"/>
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<output name="out" num_pins="72"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
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<pinlocations pattern="spread"/>
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</tile>
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<tile name="memory" height="6">
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<equivalent_sites>
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<site pb_type="memory"/>
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</equivalent_sites>
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<input name="addr1" num_pins="15"/>
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<input name="addr2" num_pins="15"/>
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<input name="data" num_pins="64"/>
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<input name="we1" num_pins="1"/>
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<input name="we2" num_pins="1"/>
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<output name="out" num_pins="64"/>
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<clock name="clk" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
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<pinlocations pattern="spread"/>
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</tile>
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</tiles>
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<!-- ODIN II specific config ends -->
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<!-- Physical descriptions begin -->
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<layout>
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<auto_layout aspect_ratio="1.0">
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<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
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<perimeter type="io" priority="100"/>
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<corners type="EMPTY" priority="101"/>
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<!--Fill with 'clb'-->
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<fill type="clb" priority="10"/>
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<!--Column of 'mult_36' with 'EMPTY' blocks wherever a 'mult_36' does not fit. Vertical offset by 1 for perimeter.-->
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<col type="mult_36" startx="6" starty="1" repeatx="8" priority="20"/>
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<col type="EMPTY" startx="6" repeatx="8" starty="1" priority="19"/>
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<!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
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<col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
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<col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
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</auto_layout>
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</layout>
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<device>
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<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
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models. We are modifying the delay values however, to include metal C and R, which allows more architecture
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experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
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(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
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45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping
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RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
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lined up with Stratix IV.
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We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
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Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
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The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
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by 2.5x when looking up in Jeff's tables.
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The delay values are lined up with Stratix IV, which has an architecture similar to this
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proposed FPGA, and which is also 40 nm
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C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
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4x minimum drive strength buffer. -->
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<sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
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<!-- Total Stratix IV tile area is about 8100 um^2, minimum width transistor area is 60 L^2 yields a tile area of 84375 MWTAs,
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Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
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This means that only 37% of our area is in the general routing, and 63% is inside the logic
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block. Note that the crossbar / local interconnect is considered part of the logic block
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area in this analysis. That is a lower proportion of of routing area than most academics
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assume, but note that the total routing area really includes the crossbar, which would push
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routing area up significantly, we estimate into the ~70% range.
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-->
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<area grid_logic_tile_area="53894"/>
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<chan_width_distr>
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<x distr="uniform" peak="1.000000"/>
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<y distr="uniform" peak="1.000000"/>
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</chan_width_distr>
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<switch_block type="wilton" fs="3"/>
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<connection_block input_switch_name="ipin_cblock"/>
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</device>
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<switchlist>
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<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
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book area formula. This means the mux transistors are about 5x minimum drive strength.
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We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
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mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
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the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
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by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified
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buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
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I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout
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(diff of second stage) listed below. Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
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The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
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2.5x when looking up in Jeff's tables.
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Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
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This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
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<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
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<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
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<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
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</switchlist>
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<segmentlist>
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<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
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With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
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reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
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<segment freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
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<mux name="0"/>
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<sb type="pattern">1 1 1 1 1</sb>
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<cb type="pattern">1 1 1 1</cb>
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</segment>
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</segmentlist>
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<complexblocklist>
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<!-- Define I/O pads begin -->
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<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
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<pb_type name="io">
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<input name="outpad" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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<clock name="clock" num_pins="1"/>
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<!-- IOs can operate as either inputs or outputs.
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Delays below come from Ian Kuon. They are small, so they should be interpreted as
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the delays to and from registers in the I/O (and generally I/Os are registered
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today and that is when you timing analyze them.
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-->
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<mode name="inpad">
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<pb_type name="inpad" blif_model=".input" num_pb="1">
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<output name="inpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="inpad" input="inpad.inpad" output="io.inpad">
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<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
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</direct>
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</interconnect>
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</mode>
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<mode name="outpad">
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<pb_type name="outpad" blif_model=".output" num_pb="1">
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<input name="outpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="outpad" input="io.outpad" output="outpad.outpad">
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<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
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</direct>
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</interconnect>
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</mode>
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<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
|
||
|
|
<!-- IOs go on the periphery of the FPGA, for consistency,
|
||
|
|
make it physically equivalent on all sides so that only one definition of I/Os is needed.
|
||
|
|
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
|
||
|
|
-->
|
||
|
|
<!-- Place I/Os on the sides of the FPGA -->
|
||
|
|
<power method="ignore"/>
|
||
|
|
</pb_type>
|
||
|
|
<!-- Define I/O pads ends -->
|
||
|
|
<!-- Define general purpose logic block (CLB) begin -->
|
||
|
|
<pb_type name="clb">
|
||
|
|
<input name="I" num_pins="33" equivalent="full"/>
|
||
|
|
<output name="O" num_pins="20" equivalent="none"/>
|
||
|
|
<clock name="clk" num_pins="1"/>
|
||
|
|
<!-- Describe fracturable logic element.
|
||
|
|
Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
|
||
|
|
The outputs of the fracturable logic element can be optionally registered
|
||
|
|
-->
|
||
|
|
<pb_type name="fle" num_pb="10">
|
||
|
|
<input name="in" num_pins="6"/>
|
||
|
|
<output name="out" num_pins="2"/>
|
||
|
|
<clock name="clk" num_pins="1"/>
|
||
|
|
<!-- Dual 5-LUT mode definition begin -->
|
||
|
|
<mode name="n2_lut5">
|
||
|
|
<pb_type name="lut5inter" num_pb="1">
|
||
|
|
<input name="in" num_pins="5"/>
|
||
|
|
<output name="out" num_pins="2"/>
|
||
|
|
<clock name="clk" num_pins="1"/>
|
||
|
|
<pb_type name="ble5" num_pb="2">
|
||
|
|
<input name="in" num_pins="5"/>
|
||
|
|
<output name="out" num_pins="1"/>
|
||
|
|
<clock name="clk" num_pins="1"/>
|
||
|
|
<!-- Define the LUT -->
|
||
|
|
<pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
|
||
|
|
<input name="in" num_pins="5" port_class="lut_in"/>
|
||
|
|
<output name="out" num_pins="1" port_class="lut_out"/>
|
||
|
|
<!-- LUT timing using delay matrix -->
|
||
|
|
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
|
||
|
|
we instead take the average of these numbers to get more stable results
|
||
|
|
82e-12
|
||
|
|
173e-12
|
||
|
|
261e-12
|
||
|
|
263e-12
|
||
|
|
398e-12
|
||
|
|
-->
|
||
|
|
<delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
|
||
|
|
235e-12
|
||
|
|
235e-12
|
||
|
|
235e-12
|
||
|
|
235e-12
|
||
|
|
235e-12
|
||
|
|
</delay_matrix>
|
||
|
|
</pb_type>
|
||
|
|
<!-- Define the flip-flop -->
|
||
|
|
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
|
||
|
|
<input name="D" num_pins="1" port_class="D"/>
|
||
|
|
<output name="Q" num_pins="1" port_class="Q"/>
|
||
|
|
<clock name="clk" num_pins="1" port_class="clock"/>
|
||
|
|
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||
|
|
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||
|
|
</pb_type>
|
||
|
|
<interconnect>
|
||
|
|
<direct name="direct1" input="ble5.in[4:0]" output="lut5[0:0].in[4:0]"/>
|
||
|
|
<direct name="direct2" input="lut5[0:0].out" output="ff[0:0].D">
|
||
|
|
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
|
||
|
|
<pack_pattern name="ble5" in_port="lut5[0:0].out" out_port="ff[0:0].D"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="direct3" input="ble5.clk" output="ff[0:0].clk"/>
|
||
|
|
<mux name="mux1" input="ff[0:0].Q lut5.out[0:0]" output="ble5.out[0:0]">
|
||
|
|
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||
|
|
<delay_constant max="25e-12" in_port="lut5.out[0:0]" out_port="ble5.out[0:0]"/>
|
||
|
|
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble5.out[0:0]"/>
|
||
|
|
</mux>
|
||
|
|
</interconnect>
|
||
|
|
</pb_type>
|
||
|
|
<interconnect>
|
||
|
|
<direct name="direct1" input="lut5inter.in" output="ble5[0:0].in"/>
|
||
|
|
<direct name="direct2" input="lut5inter.in" output="ble5[1:1].in"/>
|
||
|
|
<direct name="direct3" input="ble5[1:0].out" output="lut5inter.out"/>
|
||
|
|
<complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/>
|
||
|
|
</interconnect>
|
||
|
|
</pb_type>
|
||
|
|
<interconnect>
|
||
|
|
<direct name="direct1" input="fle.in[4:0]" output="lut5inter.in"/>
|
||
|
|
<direct name="direct2" input="lut5inter.out" output="fle.out"/>
|
||
|
|
<direct name="direct3" input="fle.clk" output="lut5inter.clk"/>
|
||
|
|
</interconnect>
|
||
|
|
</mode>
|
||
|
|
<!-- Dual 5-LUT mode definition end -->
|
||
|
|
<!-- 6-LUT mode definition begin -->
|
||
|
|
<mode name="n1_lut6">
|
||
|
|
<!-- Define 6-LUT mode -->
|
||
|
|
<pb_type name="ble6" num_pb="1">
|
||
|
|
<input name="in" num_pins="6"/>
|
||
|
|
<output name="out" num_pins="1"/>
|
||
|
|
<clock name="clk" num_pins="1"/>
|
||
|
|
<!-- Define LUT -->
|
||
|
|
<pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
|
||
|
|
<input name="in" num_pins="6" port_class="lut_in"/>
|
||
|
|
<output name="out" num_pins="1" port_class="lut_out"/>
|
||
|
|
<!-- LUT timing using delay matrix -->
|
||
|
|
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
|
||
|
|
we instead take the average of these numbers to get more stable results
|
||
|
|
82e-12
|
||
|
|
173e-12
|
||
|
|
261e-12
|
||
|
|
263e-12
|
||
|
|
398e-12
|
||
|
|
397e-12
|
||
|
|
-->
|
||
|
|
<delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
|
||
|
|
261e-12
|
||
|
|
261e-12
|
||
|
|
261e-12
|
||
|
|
261e-12
|
||
|
|
261e-12
|
||
|
|
261e-12
|
||
|
|
</delay_matrix>
|
||
|
|
</pb_type>
|
||
|
|
<!-- Define flip-flop -->
|
||
|
|
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
|
||
|
|
<input name="D" num_pins="1" port_class="D"/>
|
||
|
|
<output name="Q" num_pins="1" port_class="Q"/>
|
||
|
|
<clock name="clk" num_pins="1" port_class="clock"/>
|
||
|
|
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||
|
|
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||
|
|
</pb_type>
|
||
|
|
<interconnect>
|
||
|
|
<direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
|
||
|
|
<direct name="direct2" input="lut6.out" output="ff.D">
|
||
|
|
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
|
||
|
|
<pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="direct3" input="ble6.clk" output="ff.clk"/>
|
||
|
|
<mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
|
||
|
|
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||
|
|
<delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
|
||
|
|
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
|
||
|
|
</mux>
|
||
|
|
</interconnect>
|
||
|
|
</pb_type>
|
||
|
|
<interconnect>
|
||
|
|
<direct name="direct1" input="fle.in" output="ble6.in"/>
|
||
|
|
<direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
|
||
|
|
<direct name="direct3" input="fle.clk" output="ble6.clk"/>
|
||
|
|
</interconnect>
|
||
|
|
</mode>
|
||
|
|
<!-- 6-LUT mode definition end -->
|
||
|
|
</pb_type>
|
||
|
|
<interconnect>
|
||
|
|
<!-- We use a full crossbar to get logical equivalence at inputs of CLB
|
||
|
|
The delays below come from Stratix IV. the delay through a connection block
|
||
|
|
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
|
||
|
|
delay on the connection block input mux (modeled by Ian Kuon), so the remaining
|
||
|
|
delay within the crossbar is 95 ps.
|
||
|
|
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
|
||
|
|
Since all our outputs LUT outputs go to a BLE output, and have a delay of
|
||
|
|
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
|
||
|
|
to get the part that should be marked on the crossbar. -->
|
||
|
|
<complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
|
||
|
|
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
|
||
|
|
<delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
|
||
|
|
</complete>
|
||
|
|
<complete name="clks" input="clb.clk" output="fle[9:0].clk">
|
||
|
|
</complete>
|
||
|
|
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
|
||
|
|
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
|
||
|
|
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
|
||
|
|
naive specification).
|
||
|
|
-->
|
||
|
|
<direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
|
||
|
|
<direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
|
||
|
|
</interconnect>
|
||
|
|
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
|
||
|
|
<!-- Place this general purpose logic block in any unspecified column -->
|
||
|
|
</pb_type>
|
||
|
|
<!-- Define general purpose logic block (CLB) ends -->
|
||
|
|
<!-- Define fracturable multiplier begin -->
|
||
|
|
<!-- This multiplier can operate as a 36x36 multiplier that can fracture to two 18x18 multipliers each of which can further fracture to two 9x9 multipliers
|
||
|
|
For delay modelling, the 36x36 DSP multiplier in Stratix IV has a delay of 1.523 ns + 1.93 ns
|
||
|
|
= 3.45 ns. The 18x18 mode doesn't need to sum four 18x18 multipliers, so it is a bit
|
||
|
|
faster: 1.523 ns for the multiplier, and 1.09 ns for the multiplier output block.
|
||
|
|
For the input and output interconnect delays, unlike Stratix IV, we don't
|
||
|
|
have any routing/logic flexibility (crossbars) at the inputs. There is some output muxing
|
||
|
|
in Stratix IV and this architecture to select which multiplier outputs should go out (e.g.
|
||
|
|
9x9 outputs, 18x18 or 36x36) so those are very close between the two architectures.
|
||
|
|
We take the conservative (slightly pessimistic)
|
||
|
|
approach modelling the input as the same as the Stratix IV input delay and the output delay the same as the Stratix IV DSP out delay.
|
||
|
|
-->
|
||
|
|
<pb_type name="mult_36">
|
||
|
|
<input name="a" num_pins="36"/>
|
||
|
|
<input name="b" num_pins="36"/>
|
||
|
|
<output name="out" num_pins="72"/>
|
||
|
|
<mode name="two_divisible_mult_18x18">
|
||
|
|
<pb_type name="divisible_mult_18x18" num_pb="2">
|
||
|
|
<input name="a" num_pins="18"/>
|
||
|
|
<input name="b" num_pins="18"/>
|
||
|
|
<output name="out" num_pins="36"/>
|
||
|
|
<!-- Model 9x9 delay and 18x18 delay as the same. 9x9 could be faster, but in Stratix IV
|
||
|
|
isn't, presumably because the multiplier layout is really optimized for 18x18.
|
||
|
|
-->
|
||
|
|
<mode name="two_mult_9x9">
|
||
|
|
<pb_type name="mult_9x9_slice" num_pb="2">
|
||
|
|
<input name="A_cfg" num_pins="9"/>
|
||
|
|
<input name="B_cfg" num_pins="9"/>
|
||
|
|
<output name="OUT_cfg" num_pins="18"/>
|
||
|
|
<pb_type name="mult_9x9" blif_model=".subckt multiply" num_pb="1">
|
||
|
|
<input name="a" num_pins="9"/>
|
||
|
|
<input name="b" num_pins="9"/>
|
||
|
|
<output name="out" num_pins="18"/>
|
||
|
|
<delay_constant max="1.523e-9" in_port="mult_9x9.a" out_port="mult_9x9.out"/>
|
||
|
|
<delay_constant max="1.523e-9" in_port="mult_9x9.b" out_port="mult_9x9.out"/>
|
||
|
|
</pb_type>
|
||
|
|
<interconnect>
|
||
|
|
<direct name="a2a" input="mult_9x9_slice.A_cfg" output="mult_9x9.a">
|
||
|
|
</direct>
|
||
|
|
<direct name="b2b" input="mult_9x9_slice.B_cfg" output="mult_9x9.b">
|
||
|
|
</direct>
|
||
|
|
<direct name="out2out" input="mult_9x9.out" output="mult_9x9_slice.OUT_cfg">
|
||
|
|
</direct>
|
||
|
|
</interconnect>
|
||
|
|
<power method="pin-toggle">
|
||
|
|
<port name="A_cfg" energy_per_toggle="1.45e-12"/>
|
||
|
|
<port name="B_cfg" energy_per_toggle="1.45e-12"/>
|
||
|
|
<static_power power_per_instance="0.0"/>
|
||
|
|
</power>
|
||
|
|
</pb_type>
|
||
|
|
<interconnect>
|
||
|
|
<direct name="a2a" input="divisible_mult_18x18.a" output="mult_9x9_slice[1:0].A_cfg">
|
||
|
|
</direct>
|
||
|
|
<direct name="b2b" input="divisible_mult_18x18.b" output="mult_9x9_slice[1:0].B_cfg">
|
||
|
|
</direct>
|
||
|
|
<direct name="out2out" input="mult_9x9_slice[1:0].OUT_cfg" output="divisible_mult_18x18.out">
|
||
|
|
</direct>
|
||
|
|
</interconnect>
|
||
|
|
</mode>
|
||
|
|
<mode name="mult_18x18">
|
||
|
|
<pb_type name="mult_18x18_slice" num_pb="1">
|
||
|
|
<input name="A_cfg" num_pins="18"/>
|
||
|
|
<input name="B_cfg" num_pins="18"/>
|
||
|
|
<output name="OUT_cfg" num_pins="36"/>
|
||
|
|
<pb_type name="mult_18x18" blif_model=".subckt multiply" num_pb="1">
|
||
|
|
<input name="a" num_pins="18"/>
|
||
|
|
<input name="b" num_pins="18"/>
|
||
|
|
<output name="out" num_pins="36"/>
|
||
|
|
<delay_constant max="1.523e-9" in_port="mult_18x18.a" out_port="mult_18x18.out"/>
|
||
|
|
<delay_constant max="1.523e-9" in_port="mult_18x18.b" out_port="mult_18x18.out"/>
|
||
|
|
</pb_type>
|
||
|
|
<interconnect>
|
||
|
|
<direct name="a2a" input="mult_18x18_slice.A_cfg" output="mult_18x18.a">
|
||
|
|
</direct>
|
||
|
|
<direct name="b2b" input="mult_18x18_slice.B_cfg" output="mult_18x18.b">
|
||
|
|
</direct>
|
||
|
|
<direct name="out2out" input="mult_18x18.out" output="mult_18x18_slice.OUT_cfg">
|
||
|
|
</direct>
|
||
|
|
</interconnect>
|
||
|
|
<power method="pin-toggle">
|
||
|
|
<port name="A_cfg" energy_per_toggle="1.09e-12"/>
|
||
|
|
<port name="B_cfg" energy_per_toggle="1.09e-12"/>
|
||
|
|
<static_power power_per_instance="0.0"/>
|
||
|
|
</power>
|
||
|
|
</pb_type>
|
||
|
|
<interconnect>
|
||
|
|
<direct name="a2a" input="divisible_mult_18x18.a" output="mult_18x18_slice.A_cfg">
|
||
|
|
</direct>
|
||
|
|
<direct name="b2b" input="divisible_mult_18x18.b" output="mult_18x18_slice.B_cfg">
|
||
|
|
</direct>
|
||
|
|
<direct name="out2out" input="mult_18x18_slice.OUT_cfg" output="divisible_mult_18x18.out">
|
||
|
|
</direct>
|
||
|
|
</interconnect>
|
||
|
|
</mode>
|
||
|
|
<power method="sum-of-children"/>
|
||
|
|
</pb_type>
|
||
|
|
<interconnect>
|
||
|
|
<!-- Stratix IV input delay of 207ps is conservative for this architecture because this architecture does not have an input crossbar in the multiplier.
|
||
|
|
Subtract 72.5 ps delay, which is already in the connection block input mux, leading
|
||
|
|
-->
|
||
|
|
<direct name="a2a" input="mult_36.a" output="divisible_mult_18x18[1:0].a">
|
||
|
|
<delay_constant max="134e-12" in_port="mult_36.a" out_port="divisible_mult_18x18[1:0].a"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="b2b" input="mult_36.b" output="divisible_mult_18x18[1:0].b">
|
||
|
|
<delay_constant max="134e-12" in_port="mult_36.b" out_port="divisible_mult_18x18[1:0].b"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="out2out" input="divisible_mult_18x18[1:0].out" output="mult_36.out">
|
||
|
|
<delay_constant max="1.09e-9" in_port="divisible_mult_18x18[1:0].out" out_port="mult_36.out"/>
|
||
|
|
</direct>
|
||
|
|
</interconnect>
|
||
|
|
</mode>
|
||
|
|
<mode name="mult_36x36">
|
||
|
|
<pb_type name="mult_36x36_slice" num_pb="1">
|
||
|
|
<input name="A_cfg" num_pins="36"/>
|
||
|
|
<input name="B_cfg" num_pins="36"/>
|
||
|
|
<output name="OUT_cfg" num_pins="72"/>
|
||
|
|
<pb_type name="mult_36x36" blif_model=".subckt multiply" num_pb="1">
|
||
|
|
<input name="a" num_pins="36"/>
|
||
|
|
<input name="b" num_pins="36"/>
|
||
|
|
<output name="out" num_pins="72"/>
|
||
|
|
<delay_constant max="1.523e-9" in_port="mult_36x36.a" out_port="mult_36x36.out"/>
|
||
|
|
<delay_constant max="1.523e-9" in_port="mult_36x36.b" out_port="mult_36x36.out"/>
|
||
|
|
</pb_type>
|
||
|
|
<interconnect>
|
||
|
|
<direct name="a2a" input="mult_36x36_slice.A_cfg" output="mult_36x36.a">
|
||
|
|
</direct>
|
||
|
|
<direct name="b2b" input="mult_36x36_slice.B_cfg" output="mult_36x36.b">
|
||
|
|
</direct>
|
||
|
|
<direct name="out2out" input="mult_36x36.out" output="mult_36x36_slice.OUT_cfg">
|
||
|
|
</direct>
|
||
|
|
</interconnect>
|
||
|
|
<power method="pin-toggle">
|
||
|
|
<port name="A_cfg" energy_per_toggle="2.13e-12"/>
|
||
|
|
<port name="B_cfg" energy_per_toggle="2.13e-12"/>
|
||
|
|
<static_power power_per_instance="0.0"/>
|
||
|
|
</power>
|
||
|
|
</pb_type>
|
||
|
|
<interconnect>
|
||
|
|
<!-- Stratix IV input delay of 207ps is conservative for this architecture because this architecture does not have an input crossbar in the multiplier.
|
||
|
|
Subtract 72.5 ps delay, which is already in the connection block input mux, leading
|
||
|
|
to a 134 ps delay.
|
||
|
|
-->
|
||
|
|
<direct name="a2a" input="mult_36.a" output="mult_36x36_slice.A_cfg">
|
||
|
|
<delay_constant max="134e-12" in_port="mult_36.a" out_port="mult_36x36_slice.A_cfg"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="b2b" input="mult_36.b" output="mult_36x36_slice.B_cfg">
|
||
|
|
<delay_constant max="134e-12" in_port="mult_36.b" out_port="mult_36x36_slice.B_cfg"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="out2out" input="mult_36x36_slice.OUT_cfg" output="mult_36.out">
|
||
|
|
<delay_constant max="1.93e-9" in_port="mult_36x36_slice.OUT_cfg" out_port="mult_36.out"/>
|
||
|
|
</direct>
|
||
|
|
</interconnect>
|
||
|
|
</mode>
|
||
|
|
<!-- Place this multiplier block every 8 columns from (and including) the sixth column -->
|
||
|
|
<power method="sum-of-children"/>
|
||
|
|
</pb_type>
|
||
|
|
<!-- Define fracturable multiplier end -->
|
||
|
|
<!-- Define fracturable memory begin -->
|
||
|
|
<!-- 32 Kb Memory that can operate from 512x64 to 32Kx1 for single-port mode and 1024x32 to 32Kx1 for dual-port mode.
|
||
|
|
Area and delay based off Stratix IV 9K and 144K memories (delay from linear interpolation, Tsu(483 ps, 636 ps) Tco(1084ps, 1969ps)).
|
||
|
|
Input delay = 204ps (from Stratix IV LAB line) - 72ps (this architecture does not lump connection box delay in internal delay)
|
||
|
|
Output delay = M4K buffer 50ps
|
||
|
|
-->
|
||
|
|
<pb_type name="memory">
|
||
|
|
<input name="addr1" num_pins="15"/>
|
||
|
|
<input name="addr2" num_pins="15"/>
|
||
|
|
<input name="data" num_pins="64"/>
|
||
|
|
<input name="we1" num_pins="1"/>
|
||
|
|
<input name="we2" num_pins="1"/>
|
||
|
|
<output name="out" num_pins="64"/>
|
||
|
|
<clock name="clk" num_pins="1"/>
|
||
|
|
<!-- Specify single port mode first -->
|
||
|
|
<mode name="mem_512x64_sp">
|
||
|
|
<pb_type name="mem_512x64_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
|
||
|
|
<input name="addr" num_pins="9" port_class="address"/>
|
||
|
|
<input name="data" num_pins="64" port_class="data_in"/>
|
||
|
|
<input name="we" num_pins="1" port_class="write_en"/>
|
||
|
|
<output name="out" num_pins="64" port_class="data_out"/>
|
||
|
|
<clock name="clk" num_pins="1" port_class="clock"/>
|
||
|
|
<T_setup value="509e-12" port="mem_512x64_sp.addr" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_512x64_sp.data" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_512x64_sp.we" clock="clk"/>
|
||
|
|
<T_clock_to_Q max="1.234e-9" port="mem_512x64_sp.out" clock="clk"/>
|
||
|
|
<power method="pin-toggle">
|
||
|
|
<port name="clk" energy_per_toggle="9.0e-12"/>
|
||
|
|
<static_power power_per_instance="0.0"/>
|
||
|
|
</power>
|
||
|
|
</pb_type>
|
||
|
|
<interconnect>
|
||
|
|
<direct name="address1" input="memory.addr1[8:0]" output="mem_512x64_sp.addr">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.addr1[8:0]" out_port="mem_512x64_sp.addr"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="data1" input="memory.data[63:0]" output="mem_512x64_sp.data">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.data[63:0]" out_port="mem_512x64_sp.data"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="writeen1" input="memory.we1" output="mem_512x64_sp.we">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.we1" out_port="mem_512x64_sp.we"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="dataout1" input="mem_512x64_sp.out" output="memory.out[63:0]">
|
||
|
|
<delay_constant max="40e-12" in_port="mem_512x64_sp.out" out_port="memory.out[63:0]"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="clk" input="memory.clk" output="mem_512x64_sp.clk">
|
||
|
|
</direct>
|
||
|
|
</interconnect>
|
||
|
|
</mode>
|
||
|
|
<mode name="mem_1024x32_sp">
|
||
|
|
<pb_type name="mem_1024x32_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
|
||
|
|
<input name="addr" num_pins="10" port_class="address"/>
|
||
|
|
<input name="data" num_pins="32" port_class="data_in"/>
|
||
|
|
<input name="we" num_pins="1" port_class="write_en"/>
|
||
|
|
<output name="out" num_pins="32" port_class="data_out"/>
|
||
|
|
<clock name="clk" num_pins="1" port_class="clock"/>
|
||
|
|
<T_setup value="509e-12" port="mem_1024x32_sp.addr" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_1024x32_sp.data" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_1024x32_sp.we" clock="clk"/>
|
||
|
|
<T_clock_to_Q max="1.234e-9" port="mem_1024x32_sp.out" clock="clk"/>
|
||
|
|
<power method="pin-toggle">
|
||
|
|
<port name="clk" energy_per_toggle="9.0e-12"/>
|
||
|
|
<static_power power_per_instance="0.0"/>
|
||
|
|
</power>
|
||
|
|
</pb_type>
|
||
|
|
<interconnect>
|
||
|
|
<direct name="address1" input="memory.addr1[9:0]" output="mem_1024x32_sp.addr">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.addr1[9:0]" out_port="mem_1024x32_sp.addr"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="data1" input="memory.data[31:0]" output="mem_1024x32_sp.data">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.data[31:0]" out_port="mem_1024x32_sp.data"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="writeen1" input="memory.we1" output="mem_1024x32_sp.we">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.we1" out_port="mem_1024x32_sp.we"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="dataout1" input="mem_1024x32_sp.out" output="memory.out[31:0]">
|
||
|
|
<delay_constant max="40e-12" in_port="mem_1024x32_sp.out" out_port="memory.out[31:0]"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="clk" input="memory.clk" output="mem_1024x32_sp.clk">
|
||
|
|
</direct>
|
||
|
|
</interconnect>
|
||
|
|
</mode>
|
||
|
|
<mode name="mem_2048x16_sp">
|
||
|
|
<pb_type name="mem_2048x16_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
|
||
|
|
<input name="addr" num_pins="11" port_class="address"/>
|
||
|
|
<input name="data" num_pins="16" port_class="data_in"/>
|
||
|
|
<input name="we" num_pins="1" port_class="write_en"/>
|
||
|
|
<output name="out" num_pins="16" port_class="data_out"/>
|
||
|
|
<clock name="clk" num_pins="1" port_class="clock"/>
|
||
|
|
<T_setup value="509e-12" port="mem_2048x16_sp.addr" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_2048x16_sp.data" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_2048x16_sp.we" clock="clk"/>
|
||
|
|
<T_clock_to_Q max="1.234e-9" port="mem_2048x16_sp.out" clock="clk"/>
|
||
|
|
<power method="pin-toggle">
|
||
|
|
<port name="clk" energy_per_toggle="9.0e-12"/>
|
||
|
|
<static_power power_per_instance="0.0"/>
|
||
|
|
</power>
|
||
|
|
</pb_type>
|
||
|
|
<interconnect>
|
||
|
|
<direct name="address1" input="memory.addr1[10:0]" output="mem_2048x16_sp.addr">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.addr1[10:0]" out_port="mem_2048x16_sp.addr"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="data1" input="memory.data[15:0]" output="mem_2048x16_sp.data">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.data[15:0]" out_port="mem_2048x16_sp.data"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="writeen1" input="memory.we1" output="mem_2048x16_sp.we">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.we1" out_port="mem_2048x16_sp.we"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="dataout1" input="mem_2048x16_sp.out" output="memory.out[15:0]">
|
||
|
|
<delay_constant max="40e-12" in_port="mem_2048x16_sp.out" out_port="memory.out[15:0]"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="clk" input="memory.clk" output="mem_2048x16_sp.clk">
|
||
|
|
</direct>
|
||
|
|
</interconnect>
|
||
|
|
</mode>
|
||
|
|
<mode name="mem_4096x8_sp">
|
||
|
|
<pb_type name="mem_4096x8_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
|
||
|
|
<input name="addr" num_pins="12" port_class="address"/>
|
||
|
|
<input name="data" num_pins="8" port_class="data_in"/>
|
||
|
|
<input name="we" num_pins="1" port_class="write_en"/>
|
||
|
|
<output name="out" num_pins="8" port_class="data_out"/>
|
||
|
|
<clock name="clk" num_pins="1" port_class="clock"/>
|
||
|
|
<T_setup value="509e-12" port="mem_4096x8_sp.addr" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_4096x8_sp.data" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_4096x8_sp.we" clock="clk"/>
|
||
|
|
<T_clock_to_Q max="1.234e-9" port="mem_4096x8_sp.out" clock="clk"/>
|
||
|
|
<power method="pin-toggle">
|
||
|
|
<port name="clk" energy_per_toggle="9.0e-12"/>
|
||
|
|
<static_power power_per_instance="0.0"/>
|
||
|
|
</power>
|
||
|
|
</pb_type>
|
||
|
|
<interconnect>
|
||
|
|
<direct name="address1" input="memory.addr1[11:0]" output="mem_4096x8_sp.addr">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.addr1[11:0]" out_port="mem_4096x8_sp.addr"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="data1" input="memory.data[7:0]" output="mem_4096x8_sp.data">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.data[7:0]" out_port="mem_4096x8_sp.data"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="writeen1" input="memory.we1" output="mem_4096x8_sp.we">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.we1" out_port="mem_4096x8_sp.we"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="dataout1" input="mem_4096x8_sp.out" output="memory.out[7:0]">
|
||
|
|
<delay_constant max="40e-12" in_port="mem_4096x8_sp.out" out_port="memory.out[7:0]"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="clk" input="memory.clk" output="mem_4096x8_sp.clk">
|
||
|
|
</direct>
|
||
|
|
</interconnect>
|
||
|
|
</mode>
|
||
|
|
<mode name="mem_8192x4_sp">
|
||
|
|
<pb_type name="mem_8192x4_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
|
||
|
|
<input name="addr" num_pins="13" port_class="address"/>
|
||
|
|
<input name="data" num_pins="4" port_class="data_in"/>
|
||
|
|
<input name="we" num_pins="1" port_class="write_en"/>
|
||
|
|
<output name="out" num_pins="4" port_class="data_out"/>
|
||
|
|
<clock name="clk" num_pins="1" port_class="clock"/>
|
||
|
|
<T_setup value="509e-12" port="mem_8192x4_sp.addr" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_8192x4_sp.data" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_8192x4_sp.we" clock="clk"/>
|
||
|
|
<T_clock_to_Q max="1.234e-9" port="mem_8192x4_sp.out" clock="clk"/>
|
||
|
|
<power method="pin-toggle">
|
||
|
|
<port name="clk" energy_per_toggle="9.0e-12"/>
|
||
|
|
<static_power power_per_instance="0.0"/>
|
||
|
|
</power>
|
||
|
|
</pb_type>
|
||
|
|
<interconnect>
|
||
|
|
<direct name="address1" input="memory.addr1[12:0]" output="mem_8192x4_sp.addr">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.addr1[12:0]" out_port="mem_8192x4_sp.addr"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="data1" input="memory.data[3:0]" output="mem_8192x4_sp.data">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.data[3:0]" out_port="mem_8192x4_sp.data"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="writeen1" input="memory.we1" output="mem_8192x4_sp.we">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.we1" out_port="mem_8192x4_sp.we"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="dataout1" input="mem_8192x4_sp.out" output="memory.out[3:0]">
|
||
|
|
<delay_constant max="40e-12" in_port="mem_8192x4_sp.out" out_port="memory.out[3:0]"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="clk" input="memory.clk" output="mem_8192x4_sp.clk">
|
||
|
|
</direct>
|
||
|
|
</interconnect>
|
||
|
|
</mode>
|
||
|
|
<mode name="mem_16384x2_sp">
|
||
|
|
<pb_type name="mem_16384x2_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
|
||
|
|
<input name="addr" num_pins="14" port_class="address"/>
|
||
|
|
<input name="data" num_pins="2" port_class="data_in"/>
|
||
|
|
<input name="we" num_pins="1" port_class="write_en"/>
|
||
|
|
<output name="out" num_pins="2" port_class="data_out"/>
|
||
|
|
<clock name="clk" num_pins="1" port_class="clock"/>
|
||
|
|
<T_setup value="509e-12" port="mem_16384x2_sp.addr" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_16384x2_sp.data" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_16384x2_sp.we" clock="clk"/>
|
||
|
|
<T_clock_to_Q max="1.234e-9" port="mem_16384x2_sp.out" clock="clk"/>
|
||
|
|
<power method="pin-toggle">
|
||
|
|
<port name="clk" energy_per_toggle="9.0e-12"/>
|
||
|
|
<static_power power_per_instance="0.0"/>
|
||
|
|
</power>
|
||
|
|
</pb_type>
|
||
|
|
<interconnect>
|
||
|
|
<direct name="address1" input="memory.addr1[13:0]" output="mem_16384x2_sp.addr">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.addr1[13:0]" out_port="mem_16384x2_sp.addr"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="data1" input="memory.data[1:0]" output="mem_16384x2_sp.data">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.data[1:0]" out_port="mem_16384x2_sp.data"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="writeen1" input="memory.we1" output="mem_16384x2_sp.we">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.we1" out_port="mem_16384x2_sp.we"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="dataout1" input="mem_16384x2_sp.out" output="memory.out[1:0]">
|
||
|
|
<delay_constant max="40e-12" in_port="mem_16384x2_sp.out" out_port="memory.out[1:0]"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="clk" input="memory.clk" output="mem_16384x2_sp.clk">
|
||
|
|
</direct>
|
||
|
|
</interconnect>
|
||
|
|
</mode>
|
||
|
|
<mode name="mem_32768x1_sp">
|
||
|
|
<pb_type name="mem_32768x1_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
|
||
|
|
<input name="addr" num_pins="15" port_class="address"/>
|
||
|
|
<input name="data" num_pins="1" port_class="data_in"/>
|
||
|
|
<input name="we" num_pins="1" port_class="write_en"/>
|
||
|
|
<output name="out" num_pins="1" port_class="data_out"/>
|
||
|
|
<clock name="clk" num_pins="1" port_class="clock"/>
|
||
|
|
<T_setup value="509e-12" port="mem_32768x1_sp.addr" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_32768x1_sp.data" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_32768x1_sp.we" clock="clk"/>
|
||
|
|
<T_clock_to_Q max="1.234e-9" port="mem_32768x1_sp.out" clock="clk"/>
|
||
|
|
<power method="pin-toggle">
|
||
|
|
<port name="clk" energy_per_toggle="9.0e-12"/>
|
||
|
|
<static_power power_per_instance="0.0"/>
|
||
|
|
</power>
|
||
|
|
</pb_type>
|
||
|
|
<interconnect>
|
||
|
|
<direct name="address1" input="memory.addr1[14:0]" output="mem_32768x1_sp.addr">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.addr1[14:0]" out_port="mem_32768x1_sp.addr"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="data1" input="memory.data[0:0]" output="mem_32768x1_sp.data">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.data[0:0]" out_port="mem_32768x1_sp.data"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="writeen1" input="memory.we1" output="mem_32768x1_sp.we">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.we1" out_port="mem_32768x1_sp.we"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="dataout1" input="mem_32768x1_sp.out" output="memory.out[0:0]">
|
||
|
|
<delay_constant max="40e-12" in_port="mem_32768x1_sp.out" out_port="memory.out[0:0]"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="clk" input="memory.clk" output="mem_32768x1_sp.clk">
|
||
|
|
</direct>
|
||
|
|
</interconnect>
|
||
|
|
</mode>
|
||
|
|
<!-- Specify true dual port mode next -->
|
||
|
|
<mode name="mem_1024x32_dp">
|
||
|
|
<pb_type name="mem_1024x32_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
|
||
|
|
<input name="addr1" num_pins="10" port_class="address1"/>
|
||
|
|
<input name="addr2" num_pins="10" port_class="address2"/>
|
||
|
|
<input name="data1" num_pins="32" port_class="data_in1"/>
|
||
|
|
<input name="data2" num_pins="32" port_class="data_in2"/>
|
||
|
|
<input name="we1" num_pins="1" port_class="write_en1"/>
|
||
|
|
<input name="we2" num_pins="1" port_class="write_en2"/>
|
||
|
|
<output name="out1" num_pins="32" port_class="data_out1"/>
|
||
|
|
<output name="out2" num_pins="32" port_class="data_out2"/>
|
||
|
|
<clock name="clk" num_pins="1" port_class="clock"/>
|
||
|
|
<T_setup value="509e-12" port="mem_1024x32_dp.addr1" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_1024x32_dp.data1" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_1024x32_dp.we1" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_1024x32_dp.addr2" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_1024x32_dp.data2" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_1024x32_dp.we2" clock="clk"/>
|
||
|
|
<T_clock_to_Q max="1.234e-9" port="mem_1024x32_dp.out1" clock="clk"/>
|
||
|
|
<T_clock_to_Q max="1.234e-9" port="mem_1024x32_dp.out2" clock="clk"/>
|
||
|
|
<power method="pin-toggle">
|
||
|
|
<port name="clk" energy_per_toggle="17.9e-12"/>
|
||
|
|
<static_power power_per_instance="0.0"/>
|
||
|
|
</power>
|
||
|
|
</pb_type>
|
||
|
|
<interconnect>
|
||
|
|
<direct name="address1" input="memory.addr1[9:0]" output="mem_1024x32_dp.addr1">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.addr1[9:0]" out_port="mem_1024x32_dp.addr1"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="address2" input="memory.addr2[9:0]" output="mem_1024x32_dp.addr2">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.addr2[9:0]" out_port="mem_1024x32_dp.addr2"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="data1" input="memory.data[31:0]" output="mem_1024x32_dp.data1">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.data[31:0]" out_port="mem_1024x32_dp.data1"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="data2" input="memory.data[63:32]" output="mem_1024x32_dp.data2">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.data[63:32]" out_port="mem_1024x32_dp.data2"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="writeen1" input="memory.we1" output="mem_1024x32_dp.we1">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.we1" out_port="mem_1024x32_dp.we1"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="writeen2" input="memory.we2" output="mem_1024x32_dp.we2">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.we2" out_port="mem_1024x32_dp.we2"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="dataout1" input="mem_1024x32_dp.out1" output="memory.out[31:0]">
|
||
|
|
<delay_constant max="40e-12" in_port="mem_1024x32_dp.out1" out_port="memory.out[31:0]"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="dataout2" input="mem_1024x32_dp.out2" output="memory.out[63:32]">
|
||
|
|
<delay_constant max="40e-12" in_port="mem_1024x32_dp.out2" out_port="memory.out[63:32]"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="clk" input="memory.clk" output="mem_1024x32_dp.clk">
|
||
|
|
</direct>
|
||
|
|
</interconnect>
|
||
|
|
</mode>
|
||
|
|
<mode name="mem_2048x16_dp">
|
||
|
|
<pb_type name="mem_2048x16_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
|
||
|
|
<input name="addr1" num_pins="11" port_class="address1"/>
|
||
|
|
<input name="addr2" num_pins="11" port_class="address2"/>
|
||
|
|
<input name="data1" num_pins="16" port_class="data_in1"/>
|
||
|
|
<input name="data2" num_pins="16" port_class="data_in2"/>
|
||
|
|
<input name="we1" num_pins="1" port_class="write_en1"/>
|
||
|
|
<input name="we2" num_pins="1" port_class="write_en2"/>
|
||
|
|
<output name="out1" num_pins="16" port_class="data_out1"/>
|
||
|
|
<output name="out2" num_pins="16" port_class="data_out2"/>
|
||
|
|
<clock name="clk" num_pins="1" port_class="clock"/>
|
||
|
|
<T_setup value="509e-12" port="mem_2048x16_dp.addr1" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_2048x16_dp.data1" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_2048x16_dp.we1" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_2048x16_dp.addr2" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_2048x16_dp.data2" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_2048x16_dp.we2" clock="clk"/>
|
||
|
|
<T_clock_to_Q max="1.234e-9" port="mem_2048x16_dp.out1" clock="clk"/>
|
||
|
|
<T_clock_to_Q max="1.234e-9" port="mem_2048x16_dp.out2" clock="clk"/>
|
||
|
|
<power method="pin-toggle">
|
||
|
|
<port name="clk" energy_per_toggle="17.9e-12"/>
|
||
|
|
<static_power power_per_instance="0.0"/>
|
||
|
|
</power>
|
||
|
|
</pb_type>
|
||
|
|
<interconnect>
|
||
|
|
<direct name="address1" input="memory.addr1[10:0]" output="mem_2048x16_dp.addr1">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.addr1[10:0]" out_port="mem_2048x16_dp.addr1"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="address2" input="memory.addr2[10:0]" output="mem_2048x16_dp.addr2">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.addr2[10:0]" out_port="mem_2048x16_dp.addr2"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="data1" input="memory.data[15:0]" output="mem_2048x16_dp.data1">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.data[15:0]" out_port="mem_2048x16_dp.data1"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="data2" input="memory.data[31:16]" output="mem_2048x16_dp.data2">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.data[31:16]" out_port="mem_2048x16_dp.data2"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="writeen1" input="memory.we1" output="mem_2048x16_dp.we1">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.we1" out_port="mem_2048x16_dp.we1"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="writeen2" input="memory.we2" output="mem_2048x16_dp.we2">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.we2" out_port="mem_2048x16_dp.we2"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="dataout1" input="mem_2048x16_dp.out1" output="memory.out[15:0]">
|
||
|
|
<delay_constant max="40e-12" in_port="mem_2048x16_dp.out1" out_port="memory.out[15:0]"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="dataout2" input="mem_2048x16_dp.out2" output="memory.out[31:16]">
|
||
|
|
<delay_constant max="40e-12" in_port="mem_2048x16_dp.out2" out_port="memory.out[31:16]"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="clk" input="memory.clk" output="mem_2048x16_dp.clk">
|
||
|
|
</direct>
|
||
|
|
</interconnect>
|
||
|
|
</mode>
|
||
|
|
<mode name="mem_2048x8_dp">
|
||
|
|
<pb_type name="mem_2048x8_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
|
||
|
|
<input name="addr1" num_pins="12" port_class="address1"/>
|
||
|
|
<input name="addr2" num_pins="12" port_class="address2"/>
|
||
|
|
<input name="data1" num_pins="8" port_class="data_in1"/>
|
||
|
|
<input name="data2" num_pins="8" port_class="data_in2"/>
|
||
|
|
<input name="we1" num_pins="1" port_class="write_en1"/>
|
||
|
|
<input name="we2" num_pins="1" port_class="write_en2"/>
|
||
|
|
<output name="out1" num_pins="8" port_class="data_out1"/>
|
||
|
|
<output name="out2" num_pins="8" port_class="data_out2"/>
|
||
|
|
<clock name="clk" num_pins="1" port_class="clock"/>
|
||
|
|
<T_setup value="509e-12" port="mem_2048x8_dp.addr1" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_2048x8_dp.data1" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_2048x8_dp.we1" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_2048x8_dp.addr2" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_2048x8_dp.data2" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_2048x8_dp.we2" clock="clk"/>
|
||
|
|
<T_clock_to_Q max="1.234e-9" port="mem_2048x8_dp.out1" clock="clk"/>
|
||
|
|
<T_clock_to_Q max="1.234e-9" port="mem_2048x8_dp.out2" clock="clk"/>
|
||
|
|
<power method="pin-toggle">
|
||
|
|
<port name="clk" energy_per_toggle="17.9e-12"/>
|
||
|
|
<static_power power_per_instance="0.0"/>
|
||
|
|
</power>
|
||
|
|
</pb_type>
|
||
|
|
<interconnect>
|
||
|
|
<direct name="address1" input="memory.addr1[11:0]" output="mem_2048x8_dp.addr1">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.addr1[11:0]" out_port="mem_2048x8_dp.addr1"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="address2" input="memory.addr2[11:0]" output="mem_2048x8_dp.addr2">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.addr2[11:0]" out_port="mem_2048x8_dp.addr2"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="data1" input="memory.data[7:0]" output="mem_2048x8_dp.data1">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.data[7:0]" out_port="mem_2048x8_dp.data1"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="data2" input="memory.data[15:8]" output="mem_2048x8_dp.data2">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.data[15:8]" out_port="mem_2048x8_dp.data2"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="writeen1" input="memory.we1" output="mem_2048x8_dp.we1">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.we1" out_port="mem_2048x8_dp.we1"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="writeen2" input="memory.we2" output="mem_2048x8_dp.we2">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.we2" out_port="mem_2048x8_dp.we2"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="dataout1" input="mem_2048x8_dp.out1" output="memory.out[7:0]">
|
||
|
|
<delay_constant max="40e-12" in_port="mem_2048x8_dp.out1" out_port="memory.out[7:0]"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="dataout2" input="mem_2048x8_dp.out2" output="memory.out[15:8]">
|
||
|
|
<delay_constant max="40e-12" in_port="mem_2048x8_dp.out2" out_port="memory.out[15:8]"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="clk" input="memory.clk" output="mem_2048x8_dp.clk">
|
||
|
|
</direct>
|
||
|
|
</interconnect>
|
||
|
|
</mode>
|
||
|
|
<mode name="mem_8192x4_dp">
|
||
|
|
<pb_type name="mem_8192x4_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
|
||
|
|
<input name="addr1" num_pins="13" port_class="address1"/>
|
||
|
|
<input name="addr2" num_pins="13" port_class="address2"/>
|
||
|
|
<input name="data1" num_pins="4" port_class="data_in1"/>
|
||
|
|
<input name="data2" num_pins="4" port_class="data_in2"/>
|
||
|
|
<input name="we1" num_pins="1" port_class="write_en1"/>
|
||
|
|
<input name="we2" num_pins="1" port_class="write_en2"/>
|
||
|
|
<output name="out1" num_pins="4" port_class="data_out1"/>
|
||
|
|
<output name="out2" num_pins="4" port_class="data_out2"/>
|
||
|
|
<clock name="clk" num_pins="1" port_class="clock"/>
|
||
|
|
<T_setup value="509e-12" port="mem_8192x4_dp.addr1" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_8192x4_dp.data1" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_8192x4_dp.we1" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_8192x4_dp.addr2" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_8192x4_dp.data2" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_8192x4_dp.we2" clock="clk"/>
|
||
|
|
<T_clock_to_Q max="1.234e-9" port="mem_8192x4_dp.out1" clock="clk"/>
|
||
|
|
<T_clock_to_Q max="1.234e-9" port="mem_8192x4_dp.out2" clock="clk"/>
|
||
|
|
<power method="pin-toggle">
|
||
|
|
<port name="clk" energy_per_toggle="17.9e-12"/>
|
||
|
|
<static_power power_per_instance="0.0"/>
|
||
|
|
</power>
|
||
|
|
</pb_type>
|
||
|
|
<interconnect>
|
||
|
|
<direct name="address1" input="memory.addr1[12:0]" output="mem_8192x4_dp.addr1">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.addr1[12:0]" out_port="mem_8192x4_dp.addr1"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="address2" input="memory.addr2[12:0]" output="mem_8192x4_dp.addr2">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.addr2[12:0]" out_port="mem_8192x4_dp.addr2"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="data1" input="memory.data[3:0]" output="mem_8192x4_dp.data1">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.data[3:0]" out_port="mem_8192x4_dp.data1"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="data2" input="memory.data[7:4]" output="mem_8192x4_dp.data2">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.data[7:4]" out_port="mem_8192x4_dp.data2"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="writeen1" input="memory.we1" output="mem_8192x4_dp.we1">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.we1" out_port="mem_8192x4_dp.we1"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="writeen2" input="memory.we2" output="mem_8192x4_dp.we2">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.we2" out_port="mem_8192x4_dp.we2"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="dataout1" input="mem_8192x4_dp.out1" output="memory.out[3:0]">
|
||
|
|
<delay_constant max="40e-12" in_port="mem_8192x4_dp.out1" out_port="memory.out[3:0]"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="dataout2" input="mem_8192x4_dp.out2" output="memory.out[7:4]">
|
||
|
|
<delay_constant max="40e-12" in_port="mem_8192x4_dp.out2" out_port="memory.out[7:4]"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="clk" input="memory.clk" output="mem_8192x4_dp.clk">
|
||
|
|
</direct>
|
||
|
|
</interconnect>
|
||
|
|
</mode>
|
||
|
|
<mode name="mem_16384x2_dp">
|
||
|
|
<pb_type name="mem_16384x2_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
|
||
|
|
<input name="addr1" num_pins="14" port_class="address1"/>
|
||
|
|
<input name="addr2" num_pins="14" port_class="address2"/>
|
||
|
|
<input name="data1" num_pins="2" port_class="data_in1"/>
|
||
|
|
<input name="data2" num_pins="2" port_class="data_in2"/>
|
||
|
|
<input name="we1" num_pins="1" port_class="write_en1"/>
|
||
|
|
<input name="we2" num_pins="1" port_class="write_en2"/>
|
||
|
|
<output name="out1" num_pins="2" port_class="data_out1"/>
|
||
|
|
<output name="out2" num_pins="2" port_class="data_out2"/>
|
||
|
|
<clock name="clk" num_pins="1" port_class="clock"/>
|
||
|
|
<T_setup value="509e-12" port="mem_16384x2_dp.addr1" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_16384x2_dp.data1" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_16384x2_dp.we1" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_16384x2_dp.addr2" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_16384x2_dp.data2" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_16384x2_dp.we2" clock="clk"/>
|
||
|
|
<T_clock_to_Q max="1.234e-9" port="mem_16384x2_dp.out1" clock="clk"/>
|
||
|
|
<T_clock_to_Q max="1.234e-9" port="mem_16384x2_dp.out2" clock="clk"/>
|
||
|
|
<power method="pin-toggle">
|
||
|
|
<port name="clk" energy_per_toggle="17.9e-12"/>
|
||
|
|
<static_power power_per_instance="0.0"/>
|
||
|
|
</power>
|
||
|
|
</pb_type>
|
||
|
|
<interconnect>
|
||
|
|
<direct name="address1" input="memory.addr1[13:0]" output="mem_16384x2_dp.addr1">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.addr1[13:0]" out_port="mem_16384x2_dp.addr1"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="address2" input="memory.addr2[13:0]" output="mem_16384x2_dp.addr2">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.addr2[13:0]" out_port="mem_16384x2_dp.addr2"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="data1" input="memory.data[1:0]" output="mem_16384x2_dp.data1">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.data[1:0]" out_port="mem_16384x2_dp.data1"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="data2" input="memory.data[3:2]" output="mem_16384x2_dp.data2">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.data[3:2]" out_port="mem_16384x2_dp.data2"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="writeen1" input="memory.we1" output="mem_16384x2_dp.we1">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.we1" out_port="mem_16384x2_dp.we1"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="writeen2" input="memory.we2" output="mem_16384x2_dp.we2">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.we2" out_port="mem_16384x2_dp.we2"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="dataout1" input="mem_16384x2_dp.out1" output="memory.out[1:0]">
|
||
|
|
<delay_constant max="40e-12" in_port="mem_16384x2_dp.out1" out_port="memory.out[1:0]"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="dataout2" input="mem_16384x2_dp.out2" output="memory.out[3:2]">
|
||
|
|
<delay_constant max="40e-12" in_port="mem_16384x2_dp.out2" out_port="memory.out[3:2]"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="clk" input="memory.clk" output="mem_16384x2_dp.clk">
|
||
|
|
</direct>
|
||
|
|
</interconnect>
|
||
|
|
</mode>
|
||
|
|
<mode name="mem_32768x1_dp">
|
||
|
|
<pb_type name="mem_32768x1_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
|
||
|
|
<input name="addr1" num_pins="15" port_class="address1"/>
|
||
|
|
<input name="addr2" num_pins="15" port_class="address2"/>
|
||
|
|
<input name="data1" num_pins="1" port_class="data_in1"/>
|
||
|
|
<input name="data2" num_pins="1" port_class="data_in2"/>
|
||
|
|
<input name="we1" num_pins="1" port_class="write_en1"/>
|
||
|
|
<input name="we2" num_pins="1" port_class="write_en2"/>
|
||
|
|
<output name="out1" num_pins="1" port_class="data_out1"/>
|
||
|
|
<output name="out2" num_pins="1" port_class="data_out2"/>
|
||
|
|
<clock name="clk" num_pins="1" port_class="clock"/>
|
||
|
|
<T_setup value="509e-12" port="mem_32768x1_dp.addr1" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_32768x1_dp.data1" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_32768x1_dp.we1" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_32768x1_dp.addr2" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_32768x1_dp.data2" clock="clk"/>
|
||
|
|
<T_setup value="509e-12" port="mem_32768x1_dp.we2" clock="clk"/>
|
||
|
|
<T_clock_to_Q max="1.234e-9" port="mem_32768x1_dp.out1" clock="clk"/>
|
||
|
|
<T_clock_to_Q max="1.234e-9" port="mem_32768x1_dp.out2" clock="clk"/>
|
||
|
|
<power method="pin-toggle">
|
||
|
|
<port name="clk" energy_per_toggle="17.9e-12"/>
|
||
|
|
<static_power power_per_instance="0.0"/>
|
||
|
|
</power>
|
||
|
|
</pb_type>
|
||
|
|
<interconnect>
|
||
|
|
<direct name="address1" input="memory.addr1[14:0]" output="mem_32768x1_dp.addr1">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.addr1[14:0]" out_port="mem_32768x1_dp.addr1"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="address2" input="memory.addr2[14:0]" output="mem_32768x1_dp.addr2">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.addr2[14:0]" out_port="mem_32768x1_dp.addr2"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="data1" input="memory.data[0:0]" output="mem_32768x1_dp.data1">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.data[0:0]" out_port="mem_32768x1_dp.data1"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="data2" input="memory.data[1:1]" output="mem_32768x1_dp.data2">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.data[1:1]" out_port="mem_32768x1_dp.data2"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="writeen1" input="memory.we1" output="mem_32768x1_dp.we1">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.we1" out_port="mem_32768x1_dp.we1"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="writeen2" input="memory.we2" output="mem_32768x1_dp.we2">
|
||
|
|
<delay_constant max="132e-12" in_port="memory.we2" out_port="mem_32768x1_dp.we2"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="dataout1" input="mem_32768x1_dp.out1" output="memory.out[0:0]">
|
||
|
|
<delay_constant max="40e-12" in_port="mem_32768x1_dp.out1" out_port="memory.out[0:0]"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="dataout2" input="mem_32768x1_dp.out2" output="memory.out[1:1]">
|
||
|
|
<delay_constant max="40e-12" in_port="mem_32768x1_dp.out2" out_port="memory.out[1:1]"/>
|
||
|
|
</direct>
|
||
|
|
<direct name="clk" input="memory.clk" output="mem_32768x1_dp.clk">
|
||
|
|
</direct>
|
||
|
|
</interconnect>
|
||
|
|
</mode>
|
||
|
|
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
|
||
|
|
<!-- Place this memory block every 8 columns from (and including) the second column -->
|
||
|
|
<power method="sum-of-children"/>
|
||
|
|
</pb_type>
|
||
|
|
<!-- Define fracturable memory end -->
|
||
|
|
</complexblocklist>
|
||
|
|
<power>
|
||
|
|
<local_interconnect C_wire="2.5e-10"/>
|
||
|
|
</power>
|
||
|
|
<clocks>
|
||
|
|
<clock buffer_size="auto" C_wire="2.5e-10"/>
|
||
|
|
</clocks>
|
||
|
|
</architecture>
|