OpenFPGA/fpga_flow/benchmarks/FPGA_SPICE_bench/simple_spi.blif

# Benchmark "simple_spi" written by ABC on Mon Aug 29 15:33:11 2005
.model simple_spi
.inputs clk_i rst_i cyc_i stb_i we_i miso_i adr_i[0] adr_i[1] dat_i[0] \
 dat_i[1] dat_i[2] dat_i[3] dat_i[4] dat_i[5] dat_i[6] dat_i[7]
.outputs dat_o[0] dat_o[1] dat_o[2] dat_o[3] dat_o[4] dat_o[5] dat_o[6] \
 dat_o[7] ack_o inta_o sck_o mosi_o

.latch \tcnt_reg[1]_in \tcnt_reg[1]  2
.latch rfifo_gb_reg_in rfifo_gb_reg  2
.latch \tcnt_reg[0]_in \tcnt_reg[0]  2
.latch spif_reg_in   spif_reg  2
.latch \rfifo_wp_reg[1]_in \rfifo_wp_reg[1]  0
.latch \rfifo_wp_reg[0]_in \rfifo_wp_reg[0]  0
.latch \rfifo_mem_reg[1][4]_in \rfifo_mem_reg[1][4]  2
.latch \rfifo_mem_reg[1][5]_in \rfifo_mem_reg[1][5]  2
.latch \rfifo_mem_reg[1][6]_in \rfifo_mem_reg[1][6]  2
.latch \rfifo_mem_reg[1][7]_in \rfifo_mem_reg[1][7]  2
.latch \rfifo_mem_reg[1][8]_in \rfifo_mem_reg[1][8]  2
.latch \rfifo_mem_reg[2][1]_in \rfifo_mem_reg[2][1]  2
.latch \rfifo_mem_reg[2][2]_in \rfifo_mem_reg[2][2]  2
.latch \rfifo_mem_reg[2][3]_in \rfifo_mem_reg[2][3]  2
.latch \rfifo_mem_reg[2][4]_in \rfifo_mem_reg[2][4]  2
.latch \rfifo_mem_reg[2][5]_in \rfifo_mem_reg[2][5]  2
.latch \rfifo_mem_reg[2][6]_in \rfifo_mem_reg[2][6]  2
.latch \rfifo_mem_reg[2][7]_in \rfifo_mem_reg[2][7]  2
.latch \rfifo_mem_reg[2][8]_in \rfifo_mem_reg[2][8]  2
.latch \rfifo_mem_reg[1][1]_in \rfifo_mem_reg[1][1]  2
.latch \rfifo_mem_reg[1][2]_in \rfifo_mem_reg[1][2]  2
.latch \rfifo_mem_reg[1][3]_in \rfifo_mem_reg[1][3]  2
.latch \rfifo_mem_reg[3][1]_in \rfifo_mem_reg[3][1]  2
.latch \rfifo_mem_reg[3][2]_in \rfifo_mem_reg[3][2]  2
.latch \rfifo_mem_reg[3][3]_in \rfifo_mem_reg[3][3]  2
.latch \rfifo_mem_reg[3][4]_in \rfifo_mem_reg[3][4]  2
.latch \rfifo_mem_reg[3][5]_in \rfifo_mem_reg[3][5]  2
.latch \rfifo_mem_reg[3][6]_in \rfifo_mem_reg[3][6]  2
.latch \rfifo_mem_reg[3][7]_in \rfifo_mem_reg[3][7]  2
.latch \rfifo_mem_reg[3][8]_in \rfifo_mem_reg[3][8]  2
.latch \rfifo_mem_reg[0][1]_in \rfifo_mem_reg[0][1]  2
.latch \rfifo_mem_reg[0][2]_in \rfifo_mem_reg[0][2]  2
.latch \rfifo_mem_reg[0][4]_in \rfifo_mem_reg[0][4]  2
.latch \rfifo_mem_reg[0][5]_in \rfifo_mem_reg[0][5]  2
.latch \rfifo_mem_reg[0][6]_in \rfifo_mem_reg[0][6]  2
.latch \rfifo_mem_reg[0][8]_in \rfifo_mem_reg[0][8]  2
.latch \rfifo_mem_reg[0][3]_in \rfifo_mem_reg[0][3]  2
.latch \rfifo_mem_reg[0][7]_in \rfifo_mem_reg[0][7]  2
.latch sck_o_reg_in  sck_o_reg  2
.latch \state_reg[0]_in \state_reg[0]  2
.latch \bcnt_reg[0]_in \bcnt_reg[0]  2
.latch \bcnt_reg[2]_in \bcnt_reg[2]  2
.latch \clkcnt_reg[8]_in \clkcnt_reg[8]  2
.latch \treg_reg[7]_in \treg_reg[7]  2
.latch \bcnt_reg[1]_in \bcnt_reg[1]  2
.latch \treg_reg[2]_in \treg_reg[2]  2
.latch \treg_reg[3]_in \treg_reg[3]  2
.latch \treg_reg[4]_in \treg_reg[4]  2
.latch \treg_reg[5]_in \treg_reg[5]  2
.latch \treg_reg[6]_in \treg_reg[6]  2
.latch \treg_reg[0]_in \treg_reg[0]  2
.latch \treg_reg[1]_in \treg_reg[1]  2
.latch \clkcnt_reg[10]_in \clkcnt_reg[10]  2
.latch \clkcnt_reg[7]_in \clkcnt_reg[7]  2
.latch \clkcnt_reg[4]_in \clkcnt_reg[4]  2
.latch \clkcnt_reg[3]_in \clkcnt_reg[3]  2
.latch \clkcnt_reg[6]_in \clkcnt_reg[6]  2
.latch \clkcnt_reg[9]_in \clkcnt_reg[9]  2
.latch \clkcnt_reg[2]_in \clkcnt_reg[2]  2
.latch \clkcnt_reg[0]_in \clkcnt_reg[0]  2
.latch \clkcnt_reg[1]_in \clkcnt_reg[1]  2
.latch \clkcnt_reg[5]_in \clkcnt_reg[5]  2
.latch \state_reg[1]_in \state_reg[1]  2
.latch rfwe_reg_in   rfwe_reg  2
.latch \clkcnt_reg[11]_in \clkcnt_reg[11]  2
.latch \dat_o_reg[6]_in \dat_o_reg[6]  2
.latch wfifo_gb_reg_in wfifo_gb_reg  2
.latch \dat_o_reg[3]_in \dat_o_reg[3]  2
.latch \dat_o_reg[2]_in \dat_o_reg[2]  2
.latch \dat_o_reg[1]_in \dat_o_reg[1]  2
.latch \dat_o_reg[5]_in \dat_o_reg[5]  2
.latch \dat_o_reg[0]_in \dat_o_reg[0]  2
.latch wcol_reg_in   wcol_reg  2
.latch \dat_o_reg[7]_in \dat_o_reg[7]  2
.latch \dat_o_reg[4]_in \dat_o_reg[4]  2
.latch \rfifo_rp_reg[1]_in \rfifo_rp_reg[1]  0
.latch \wfifo_rp_reg[1]_in \wfifo_rp_reg[1]  0
.latch \rfifo_rp_reg[0]_in \rfifo_rp_reg[0]  0
.latch \wfifo_mem_reg[2][5]_in \wfifo_mem_reg[2][5]  2
.latch \wfifo_mem_reg[1][7]_in \wfifo_mem_reg[1][7]  2
.latch \wfifo_mem_reg[2][1]_in \wfifo_mem_reg[2][1]  2
.latch \wfifo_mem_reg[1][5]_in \wfifo_mem_reg[1][5]  2
.latch \wfifo_wp_reg[1]_in \wfifo_wp_reg[1]  0
.latch \wfifo_wp_reg[0]_in \wfifo_wp_reg[0]  0
.latch \wfifo_mem_reg[1][1]_in \wfifo_mem_reg[1][1]  2
.latch \wfifo_mem_reg[1][2]_in \wfifo_mem_reg[1][2]  2
.latch \wfifo_mem_reg[1][3]_in \wfifo_mem_reg[1][3]  2
.latch \wfifo_mem_reg[1][4]_in \wfifo_mem_reg[1][4]  2
.latch \wfifo_mem_reg[1][6]_in \wfifo_mem_reg[1][6]  2
.latch \wfifo_mem_reg[1][8]_in \wfifo_mem_reg[1][8]  2
.latch \wfifo_mem_reg[2][2]_in \wfifo_mem_reg[2][2]  2
.latch \wfifo_mem_reg[2][3]_in \wfifo_mem_reg[2][3]  2
.latch \wfifo_mem_reg[2][4]_in \wfifo_mem_reg[2][4]  2
.latch \wfifo_mem_reg[2][6]_in \wfifo_mem_reg[2][6]  2
.latch \wfifo_mem_reg[2][7]_in \wfifo_mem_reg[2][7]  2
.latch \wfifo_mem_reg[2][8]_in \wfifo_mem_reg[2][8]  2
.latch \wfifo_mem_reg[0][5]_in \wfifo_mem_reg[0][5]  2
.latch \wfifo_mem_reg[3][5]_in \wfifo_mem_reg[3][5]  2
.latch \wfifo_mem_reg[3][1]_in \wfifo_mem_reg[3][1]  2
.latch \wfifo_mem_reg[0][8]_in \wfifo_mem_reg[0][8]  2
.latch \wfifo_mem_reg[0][1]_in \wfifo_mem_reg[0][1]  2
.latch \wfifo_mem_reg[0][2]_in \wfifo_mem_reg[0][2]  2
.latch \wfifo_mem_reg[0][3]_in \wfifo_mem_reg[0][3]  2
.latch \wfifo_mem_reg[0][4]_in \wfifo_mem_reg[0][4]  2
.latch \wfifo_mem_reg[0][7]_in \wfifo_mem_reg[0][7]  2
.latch \wfifo_mem_reg[0][6]_in \wfifo_mem_reg[0][6]  2
.latch \wfifo_mem_reg[3][2]_in \wfifo_mem_reg[3][2]  2
.latch \wfifo_mem_reg[3][3]_in \wfifo_mem_reg[3][3]  2
.latch \wfifo_mem_reg[3][4]_in \wfifo_mem_reg[3][4]  2
.latch \wfifo_mem_reg[3][6]_in \wfifo_mem_reg[3][6]  2
.latch \wfifo_mem_reg[3][7]_in \wfifo_mem_reg[3][7]  2
.latch \wfifo_mem_reg[3][8]_in \wfifo_mem_reg[3][8]  2
.latch \sper_reg[5]_in \sper_reg[5]  0
.latch wfre_reg_in   wfre_reg  2
.latch \sper_reg[0]_in \sper_reg[0]  0
.latch \sper_reg[1]_in \sper_reg[1]  0
.latch \sper_reg[2]_in \sper_reg[2]  0
.latch \sper_reg[3]_in \sper_reg[3]  0
.latch \sper_reg[4]_in \sper_reg[4]  0
.latch \sper_reg[6]_in \sper_reg[6]  0
.latch \sper_reg[7]_in \sper_reg[7]  0
.latch \spcr_reg[7]_in \spcr_reg[7]  0
.latch \spcr_reg[5]_in \spcr_reg[5]  0
.latch \spcr_reg[0]_in \spcr_reg[0]  0
.latch \spcr_reg[2]_in \spcr_reg[2]  0
.latch \spcr_reg[4]_in \spcr_reg[4]  1
.latch \spcr_reg[1]_in \spcr_reg[1]  0
.latch \spcr_reg[3]_in \spcr_reg[3]  0
.latch \spcr_reg[6]_in \spcr_reg[6]  0
.latch \wfifo_rp_reg[0]_in \wfifo_rp_reg[0]  0
.latch ack_o_reg_in  ack_o_reg  0
.latch inta_o_reg_in inta_o_reg  2

.names [160]
 0
.names [161]
 1
.names \tcnt_reg[1] [162]
1 1
.names rfifo_gb_reg [163]
1 1
.names [243] [203] \tcnt_reg[1]_in
11 0
.names \tcnt_reg[0] [165]
1 1
.names spif_reg [166]
1 1
.names [574] [241] [767] rfifo_gb_reg_in
11- 0
--1 0
.names \rfifo_wp_reg[1] [168]
1 1
.names \rfifo_wp_reg[0] [169]
1 1
.names \rfifo_mem_reg[1][4] [170]
1 1
.names \rfifo_mem_reg[1][5] [171]
1 1
.names \rfifo_mem_reg[1][6] [172]
1 1
.names \rfifo_mem_reg[1][7] [173]
1 1
.names \rfifo_mem_reg[1][8] [174]
1 1
.names \rfifo_mem_reg[2][1] [175]
1 1
.names \rfifo_mem_reg[2][2] [176]
1 1
.names \rfifo_mem_reg[2][3] [177]
1 1
.names \rfifo_mem_reg[2][4] [178]
1 1
.names \rfifo_mem_reg[2][5] [179]
1 1
.names \rfifo_mem_reg[2][6] [180]
1 1
.names \rfifo_mem_reg[2][7] [181]
1 1
.names \rfifo_mem_reg[2][8] [182]
1 1
.names \rfifo_mem_reg[1][1] [183]
1 1
.names \rfifo_mem_reg[1][2] [184]
1 1
.names \rfifo_mem_reg[1][3] [185]
1 1
.names \rfifo_mem_reg[3][1] [186]
1 1
.names \rfifo_mem_reg[3][2] [187]
1 1
.names \rfifo_mem_reg[3][3] [188]
1 1
.names \rfifo_mem_reg[3][4] [189]
1 1
.names \rfifo_mem_reg[3][5] [190]
1 1
.names \rfifo_mem_reg[3][6] [191]
1 1
.names \rfifo_mem_reg[3][7] [192]
1 1
.names \rfifo_mem_reg[3][8] [193]
1 1
.names \rfifo_mem_reg[0][1] [194]
1 1
.names \rfifo_mem_reg[0][2] [195]
1 1
.names \rfifo_mem_reg[0][4] [196]
1 1
.names \rfifo_mem_reg[0][5] [197]
1 1
.names \rfifo_mem_reg[0][6] [198]
1 1
.names \rfifo_mem_reg[0][8] [199]
1 1
.names \rfifo_mem_reg[0][3] [200]
1 1
.names \rfifo_mem_reg[0][7] [201]
1 1
.names [531] [239] spif_reg_in
11 0
.names [240] [836] [203]
11 0
.names [465] [244] [831] \tcnt_reg[0]_in
01- 1
1-1 1
.names [640] [172] [272] \rfifo_mem_reg[1][6]_in
01- 1
1-1 1
.names [641] [173] [272] \rfifo_mem_reg[1][7]_in
01- 1
1-1 1
.names [650] [174] [272] \rfifo_mem_reg[1][8]_in
01- 1
1-1 1
.names [648] [175] [272] \rfifo_mem_reg[2][1]_in
01- 1
1-1 1
.names [644] [176] [272] \rfifo_mem_reg[2][2]_in
01- 1
1-1 1
.names [647] [178] [272] \rfifo_mem_reg[2][4]_in
01- 1
1-1 1
.names [646] [177] [272] \rfifo_mem_reg[2][3]_in
01- 1
1-1 1
.names [645] [179] [272] \rfifo_mem_reg[2][5]_in
01- 1
1-1 1
.names [654] [180] [272] \rfifo_mem_reg[2][6]_in
01- 1
1-1 1
.names [643] [181] [272] \rfifo_mem_reg[2][7]_in
01- 1
1-1 1
.names [651] [182] [272] \rfifo_mem_reg[2][8]_in
01- 1
1-1 1
.names [649] [183] [272] \rfifo_mem_reg[1][1]_in
01- 1
1-1 1
.names [653] [184] [272] \rfifo_mem_reg[1][2]_in
01- 1
1-1 1
.names [655] [185] [272] \rfifo_mem_reg[1][3]_in
01- 1
1-1 1
.names [705] [186] [272] \rfifo_mem_reg[3][1]_in
01- 1
1-1 1
.names [698] [187] [272] \rfifo_mem_reg[3][2]_in
01- 1
1-1 1
.names [706] [188] [272] \rfifo_mem_reg[3][3]_in
01- 1
1-1 1
.names [697] [189] [272] \rfifo_mem_reg[3][4]_in
01- 1
1-1 1
.names [701] [190] [272] \rfifo_mem_reg[3][5]_in
01- 1
1-1 1
.names [699] [191] [272] \rfifo_mem_reg[3][6]_in
01- 1
1-1 1
.names [700] [192] [272] \rfifo_mem_reg[3][7]_in
01- 1
1-1 1
.names [702] [193] [272] \rfifo_mem_reg[3][8]_in
01- 1
1-1 1
.names [743] [194] [272] \rfifo_mem_reg[0][1]_in
01- 1
1-1 1
.names [744] [195] [272] \rfifo_mem_reg[0][2]_in
01- 1
1-1 1
.names [745] [200] [272] \rfifo_mem_reg[0][3]_in
01- 1
1-1 1
.names [746] [196] [272] \rfifo_mem_reg[0][4]_in
01- 1
1-1 1
.names [736] [197] [272] \rfifo_mem_reg[0][5]_in
01- 1
1-1 1
.names [737] [198] [272] \rfifo_mem_reg[0][6]_in
01- 1
1-1 1
.names [747] [201] [272] \rfifo_mem_reg[0][7]_in
01- 1
1-1 1
.names [748] [199] [272] \rfifo_mem_reg[0][8]_in
01- 1
1-1 1
.names [248] [252] [971] \rfifo_wp_reg[1]_in
11- 0
--1 0
.names [246] [247] [971] \rfifo_wp_reg[0]_in
11- 0
--1 0
.names [652] [170] [272] \rfifo_mem_reg[1][4]_in
01- 1
1-1 1
.names [642] [171] [272] \rfifo_mem_reg[1][5]_in
01- 1
1-1 1
.names [249] [627] [876] [239]
111 0
.names [253] [245] [240]
11 0
.names [250] [722] [241]
11 0
.names sck_o_reg sck_o
1 1
.names [809] [272] [473] [844] [243]
11-- 0
--11 0
.names [776] [272] [268] [244]
00- 1
--0 1
.names [270] [853] [165] [245]
111 0
.names [882] [272] [246]
11 0
.names [882] [272] [247]
00 0
.names [168] [272] [248]
11 0
.names [272] [859] [249]
00 1
.names [685] [272] [250]
00 1
.names \state_reg[0] [251]
1 1
.names [760] [272] [252]
00 0
.names [269] [876] [253]
11 0
.names \bcnt_reg[0] [254]
1 1
.names [267] sck_o_reg_in
0 1
.names \bcnt_reg[2] [256]
1 1
.names \clkcnt_reg[8] [257]
1 1
.names \treg_reg[7] mosi_o
1 1
.names \bcnt_reg[1] [259]
1 1
.names \treg_reg[2] [260]
1 1
.names \treg_reg[3] [261]
1 1
.names \treg_reg[4] [262]
1 1
.names \treg_reg[5] [263]
1 1
.names \treg_reg[6] [264]
1 1
.names \treg_reg[0] [265]
1 1
.names \treg_reg[1] [266]
1 1
.names [932] [771] [267]
11 0
.names [165] [297] [268]
11 0
.names [297] [903] [269]
00 1
.names [297] [902] [270]
00 1
.names [279] \state_reg[0]_in
0 1
.names [285] [272]
0 1
.names [298] [333] \clkcnt_reg[8]_in
11 0
.names [414] [300] [814] \treg_reg[0]_in
11- 0
--1 0
.names [322] [975] [971] \bcnt_reg[2]_in
11- 0
--1 0
.names [415] [308] [859] \treg_reg[1]_in
11- 0
--1 0
.names [416] [309] [859] \treg_reg[2]_in
11- 0
--1 0
.names [417] [311] [859] \treg_reg[3]_in
11- 0
--1 0
.names [299] [771] [279]
11 0
.names [418] [312] [814] \treg_reg[4]_in
11- 0
--1 0
.names [419] [313] [814] \treg_reg[5]_in
11- 0
--1 0
.names [420] [314] [859] \treg_reg[6]_in
11- 0
--1 0
.names [315] [411] [814] \treg_reg[7]_in
11- 0
--1 0
.names [305] [975] [971] \bcnt_reg[1]_in
11- 0
--1 0
.names [297] [285]
0 1
.names \clkcnt_reg[10] [286]
1 1
.names \clkcnt_reg[7] [287]
1 1
.names \clkcnt_reg[4] [288]
1 1
.names \clkcnt_reg[3] [289]
1 1
.names \clkcnt_reg[6] [290]
1 1
.names \clkcnt_reg[9] [291]
1 1
.names \clkcnt_reg[2] [292]
1 1
.names \clkcnt_reg[0] [293]
1 1
.names \clkcnt_reg[1] [294]
1 1
.names \clkcnt_reg[5] [295]
1 1
.names \state_reg[1] [296]
1 1
.names rfwe_reg [297]
0 1
.names [537] [388] [324] [298]
11- 0
--1 0
.names [365] [528] [372] [758] [299]
1111 0
.names [358] [977] [265] [973] [300]
11-- 0
--11 0
.names [325] rfwe_reg_in
0 1
.names [348] [332] \clkcnt_reg[4]_in
11 0
.names [351] [334] \clkcnt_reg[0]_in
11 0
.names [350] [337] \clkcnt_reg[2]_in
11 0
.names [356] [977] [873] [973] [305]
11-- 0
--11 0
.names \clkcnt_reg[11] [306]
1 1
.names [340] [338] \clkcnt_reg[3]_in
11 0
.names [359] [977] [266] [973] [308]
11-- 0
--11 0
.names [360] [977] [260] [973] [309]
11-- 0
--11 0
.names \dat_o_reg[6] dat_o[6]
1 1
.names [361] [977] [261] [973] [311]
11-- 0
--11 0
.names [362] [977] [262] [973] [312]
11-- 0
--11 0
.names [363] [977] [263] [973] [313]
11-- 0
--11 0
.names [364] [977] [264] [973] [314]
11-- 0
--11 0
.names [357] [977] [973] mosi_o [315]
11-- 0
--11 0
.names [353] [334] \clkcnt_reg[1]_in
11 0
.names [349] [336] \clkcnt_reg[10]_in
11 0
.names [354] [332] \clkcnt_reg[5]_in
11 0
.names [335] [343] \clkcnt_reg[7]_in
11 0
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