OpenFPGA/fpga_flow/benchmarks/FPGA_SPICE_bench/router.blif

.model top
.inputs dest_x[0] dest_x[1] dest_x[2] dest_x[3] dest_x[4] dest_x[5] \
 dest_x[6] dest_x[7] dest_x[8] dest_x[9] dest_x[10] dest_x[11] dest_x[12] \
 dest_x[13] dest_x[14] dest_x[15] dest_x[16] dest_x[17] dest_x[18] \
 dest_x[19] dest_x[20] dest_x[21] dest_x[22] dest_x[23] dest_x[24] \
 dest_x[25] dest_x[26] dest_x[27] dest_x[28] dest_x[29] dest_y[0] dest_y[1] \
 dest_y[2] dest_y[3] dest_y[4] dest_y[5] dest_y[6] dest_y[7] dest_y[8] \
 dest_y[9] dest_y[10] dest_y[11] dest_y[12] dest_y[13] dest_y[14] \
 dest_y[15] dest_y[16] dest_y[17] dest_y[18] dest_y[19] dest_y[20] \
 dest_y[21] dest_y[22] dest_y[23] dest_y[24] dest_y[25] dest_y[26] \
 dest_y[27] dest_y[28] dest_y[29]
.outputs outport[0] outport[1] outport[2] outport[3] outport[4] outport[5] \
 outport[6] outport[7] outport[8] outport[9] outport[10] outport[11] \
 outport[12] outport[13] outport[14] outport[15] outport[16] outport[17] \
 outport[18] outport[19] outport[20] outport[21] outport[22] outport[23] \
 outport[24] outport[25] outport[26] outport[27] outport[28] outport[29]
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.end