185 lines
8.3 KiB
C++
185 lines
8.3 KiB
C++
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/********************************************************************
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* This file includes functions to fix up the pb pin mapping results
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* after routing optimization
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*******************************************************************/
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/* Headers from vtrutil library */
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#include "vtr_time.h"
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#include "vtr_assert.h"
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#include "vtr_log.h"
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/* Headers from vpr library */
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#include "vpr_utils.h"
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#include "pb_type_utils.h"
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#include "openfpga_pb_pin_fixup.h"
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/* Include global variables of VPR */
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#include "globals.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* Give a given pin index, find the side where this pin is located
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* on the physical tile
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* Note:
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* - Need to check if the pin_width_offset and pin_height_offset
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* are properly set in VPR!!!
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*******************************************************************/
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static
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std::vector<e_side> find_logic_tile_pin_side(t_physical_tile_type_ptr physical_tile,
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const int& physical_pin) {
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std::vector<e_side> pin_sides;
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for (const e_side& side_cand : {TOP, RIGHT, BOTTOM, LEFT}) {
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int pin_width_offset = physical_tile->pin_width_offset[physical_pin];
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int pin_height_offset = physical_tile->pin_height_offset[physical_pin];
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if (true == physical_tile->pinloc[pin_width_offset][pin_height_offset][side_cand][physical_pin]) {
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pin_sides.push_back(side_cand);
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}
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}
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return pin_sides;
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}
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/********************************************************************
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* Fix up the pb pin mapping results for a given clustered block
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* 1. For each input/output pin of a clustered pb,
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* - find a corresponding node in RRGraph object
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* - find the net id for the node in routing context
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* - find the net id for the node in clustering context
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* - if the net id does not match, we update the clustering context
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*******************************************************************/
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static
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void update_cluster_pin_with_post_routing_results(const DeviceContext& device_ctx,
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const ClusteringContext& clustering_ctx,
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const VprRoutingAnnotation& vpr_routing_annotation,
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VprClusteringAnnotation& vpr_clustering_annotation,
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const vtr::Point<size_t>& grid_coord,
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const ClusterBlockId& blk_id,
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const bool& verbose) {
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/* Handle each pin */
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auto logical_block = clustering_ctx.clb_nlist.block_type(blk_id);
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auto physical_tile = pick_best_physical_type(logical_block);
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for (int j = 0; j < logical_block->pb_type->num_pins; j++) {
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/* Get the ptc num for the pin in rr_graph */
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int physical_pin = get_physical_pin(physical_tile, logical_block, j);
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auto pin_class = physical_tile->pin_class[physical_pin];
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auto class_inf = physical_tile->class_inf[pin_class];
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t_rr_type rr_node_type;
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if (class_inf.type == DRIVER) {
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rr_node_type = OPIN;
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} else {
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VTR_ASSERT(class_inf.type == RECEIVER);
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rr_node_type = IPIN;
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}
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std::vector<e_side> pin_sides = find_logic_tile_pin_side(physical_tile, physical_pin);
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/* As some grid go across columns or rows, we may not have the pin on any side */
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if (0 == pin_sides.size()) {
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continue;
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}
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for (const e_side& pin_side : pin_sides) {
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/* Find the net mapped to this pin in routing results */
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const RRNodeId& rr_node = device_ctx.rr_graph.find_node(grid_coord.x(), grid_coord.y(), rr_node_type, physical_pin, pin_side);
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if (false == device_ctx.rr_graph.valid_node_id(rr_node)) {
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continue;
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}
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/* Get the cluster net id which has been mapped to this net */
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ClusterNetId routing_net_id = vpr_routing_annotation.rr_node_net(rr_node);
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/* Find the net mapped to this pin in clustering results*/
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ClusterNetId cluster_net_id = clustering_ctx.clb_nlist.block_net(blk_id, j);
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/* If matched, we finish here */
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if (routing_net_id == cluster_net_id) {
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continue;
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}
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/* Add to net modification */
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vpr_clustering_annotation.rename_net(blk_id, j, routing_net_id);
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std::string routing_net_name("unmapped");
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if (ClusterNetId::INVALID() != routing_net_id) {
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routing_net_name = clustering_ctx.clb_nlist.net_name(routing_net_id);
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}
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std::string cluster_net_name("unmapped");
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if (ClusterNetId::INVALID() != cluster_net_id) {
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cluster_net_name = clustering_ctx.clb_nlist.net_name(cluster_net_id);
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}
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VTR_LOGV(verbose,
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"Fixed up net '%s' mapping mismatch at clustered block '%s' pin '%s[%d]' (was net '%s')\n",
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routing_net_name.c_str(),
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clustering_ctx.clb_nlist.block_pb(blk_id)->name,
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get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->port->name,
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get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->pin_number,
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cluster_net_name.c_str()
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);
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}
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}
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}
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/********************************************************************
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* Main function to fix up the pb pin mapping results
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* This function will walk through each grid
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*******************************************************************/
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static
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void update_pb_pin_with_post_routing_results(const DeviceContext& device_ctx,
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const ClusteringContext& clustering_ctx,
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const PlacementContext& placement_ctx,
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const VprRoutingAnnotation& vpr_routing_annotation,
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VprClusteringAnnotation& vpr_clustering_annotation,
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const bool& verbose) {
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for (size_t x = 0; x < device_ctx.grid.width(); ++x) {
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for (size_t y = 0; y < device_ctx.grid.height(); ++y) {
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/* Bypass the EMPTY tiles */
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if (device_ctx.EMPTY_PHYSICAL_TILE_TYPE == device_ctx.grid[x][y].type) {
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continue;
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}
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/* Get the mapped blocks to this grid */
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for (const ClusterBlockId& cluster_blk_id : placement_ctx.grid_blocks[x][y].blocks) {
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/* Skip invalid ids */
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if (ClusterBlockId::INVALID() == cluster_blk_id) {
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continue;
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}
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/* We know the entrance to grid info and mapping results, do the fix-up for this block */
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vtr::Point<size_t> grid_coord(x, y);
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update_cluster_pin_with_post_routing_results(device_ctx, clustering_ctx,
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vpr_routing_annotation, vpr_clustering_annotation,
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grid_coord, cluster_blk_id,
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verbose);
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}
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}
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}
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}
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/********************************************************************
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* Top-level function to fix up the pb pin mapping results
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* The problem comes from a mismatch between the packing and routing results
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* When there are equivalent input/output for any grids, router will try
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* to swap the net mapping among these pins so as to achieve best
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* routing optimization.
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* However, it will cause the packing results out-of-date as the net mapping
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* of each grid remain untouched once packing is done.
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* This function aims to fix the mess after routing so that the net mapping
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* can be synchronized
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*******************************************************************/
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void pb_pin_fixup(OpenfpgaContext& openfpga_context,
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const Command& cmd, const CommandContext& cmd_context) {
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vtr::ScopedStartFinishTimer timer("Fix up pb pin mapping results after routing optimization");
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CommandOptionId opt_verbose = cmd.option("verbose");
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/* Apply fix-up to each grid */
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update_pb_pin_with_post_routing_results(g_vpr_ctx.device(),
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g_vpr_ctx.clustering(),
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g_vpr_ctx.placement(),
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openfpga_context.vpr_routing_annotation(),
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openfpga_context.mutable_vpr_clustering_annotation(),
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cmd_context.option_enable(cmd, opt_verbose));
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}
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} /* end namespace openfpga */
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