48 lines
1.6 KiB
C++
48 lines
1.6 KiB
C++
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/********************************************************************
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* This file includes functions that are used to annotate routing results
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* from VPR to OpenFPGA
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*******************************************************************/
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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#include "vtr_log.h"
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#include "annotate_routing.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* Create a mapping between each rr_node and its mapped nets
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* based on VPR routing results
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* - Unmapped rr_node will use invalid ids
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*******************************************************************/
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void annotate_rr_node_nets(const ClusteringContext& vpr_clustering_ctx,
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const RoutingContext& vpr_routing_ctx,
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VprRoutingAnnotation& vpr_routing_annotation) {
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size_t counter = 0;
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VTR_LOG("Annotating rr_node with routed nets...");
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for (auto net_id : vpr_clustering_ctx.clb_nlist.nets()) {
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/* Ignore nets that are not routed */
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if (true == vpr_clustering_ctx.clb_nlist.net_is_ignored(net_id)) {
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continue;
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}
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/* Ignore used in local cluster only, reserved one CLB pin */
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if (false == vpr_clustering_ctx.clb_nlist.net_sinks(net_id).size()) {
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continue;
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}
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t_trace* tptr = vpr_routing_ctx.trace[net_id].head;
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while (tptr != nullptr) {
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RRNodeId rr_node = tptr->index;
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vpr_routing_annotation.set_rr_node_net(rr_node, net_id);
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counter++;
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tptr = tptr->next;
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}
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}
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VTR_LOG("Done with %d nodes mapping\n", counter);
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}
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} /* end namespace openfpga */
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