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OpenFPGA/openfpga_flow/benchmarks/micro_benchmark/and2_pipelined/and2_pipelined.blif

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[Benchmark] Bug fix in pipelined and2 benchmark
2021-01-10 11:27:59 -06:00
# Benchmark "and2_pipelined" written by ABC on Sun Jan 10 10:26:01 2021
[Benchmark] Add a micro benchmark to test pipelined architecture
2021-01-10 11:21:30 -06:00
.model and2_pipelined
.inputs clk a b
.outputs c
[Benchmark] Bug fix in pipelined and2 benchmark
2021-01-10 11:27:59 -06:00
.latch n10 c 2
.latch n13 a_reg 2
.latch n17 b_reg 2
[Benchmark] Add a micro benchmark to test pipelined architecture
2021-01-10 11:21:30 -06:00
[Benchmark] Bug fix in pipelined and2 benchmark
2021-01-10 11:27:59 -06:00
.names a_reg b_reg n10
[Benchmark] Add a micro benchmark to test pipelined architecture
2021-01-10 11:21:30 -06:00
11 1
[Benchmark] Bug fix in pipelined and2 benchmark
2021-01-10 11:27:59 -06:00
.names a n13
1 1
.names b n17
1 1
[Benchmark] Add a micro benchmark to test pipelined architecture
2021-01-10 11:21:30 -06:00
.end