OpenFPGA/yosys/manual/APPNOTE_011_Design_Investig.../sumprod.v

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module sumprod(a, b, c, sum, prod);
input [7:0] a, b, c;
output [7:0] sum, prod;
{* sumstuff *}
assign sum = a + b + c;
{* *}
assign prod = a * b * c;
endmodule