11 lines
227 B
Plaintext
11 lines
227 B
Plaintext
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read_verilog test_arith.v
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synth_ice40
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techmap -map ../cells_sim.v
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rename test gate
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read_verilog test_arith.v
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rename test gold
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miter -equiv -flatten -make_outputs gold gate miter
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sat -verify -prove trigger 0 -show-ports miter
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