53 lines
1.9 KiB
C
53 lines
1.9 KiB
C
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#ifndef REPACK_OPTION_H
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#define REPACK_OPTION_H
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/********************************************************************
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* Include header files required by the data structure definition
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*******************************************************************/
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#include <string>
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#include <vector>
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#include "repack_design_constraints.h"
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/* Begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* Options for RRGSB writer
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*******************************************************************/
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class RepackOption {
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public: /* Public constructor */
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/* Set default options */
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RepackOption();
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public: /* Public accessors */
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RepackDesignConstraints design_constraints() const;
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/* Identify if a pin should ignore all the global nets */
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bool is_pin_ignore_global_nets(const std::string& pb_type_name, const BasicPort& pin) const;
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bool verbose_output() const;
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public: /* Public mutators */
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void set_design_constraints(const RepackDesignConstraints& design_constraints);
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void set_ignore_global_nets_on_pins(const std::string& content);
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void set_verbose_output(const bool& enabled);
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public: /* Public validators */
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/* Check if the following internal data is valid or not:
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* - no parsing errors
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*/
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bool valid() const;
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private: /* Internal Data */
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RepackDesignConstraints design_constraints_;
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/* The pin information on which global nets should be mapped to: [pb_type_name][0..num_ports]
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* For example:
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* - clb.I[0:1], clb.I[5:6] -> ["clb"][BasicPort(I, 0, 1), BasicPort(I, 5, 6)]
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* - clb.I[0:1], clb.I[2:6] -> ["clb"][BasicPort(I, 0, 6)]
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*/
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std::map<std::string, std::vector<BasicPort>> ignore_global_nets_on_pins_;
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bool verbose_output_;
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/* A flag to indicate if the data parse is invalid or not */
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int num_parse_errors_;
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};
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} /* End namespace openfpga*/
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#endif
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