82 lines
3.3 KiB
C++
82 lines
3.3 KiB
C++
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/********************************************************************
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* This file includes functions that outputs tile annotations to XML format
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*******************************************************************/
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/* Headers from system goes first */
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#include <string>
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#include <algorithm>
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/* Headers from vtr util library */
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#include "vtr_assert.h"
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#include "vtr_log.h"
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#include "openfpga_digest.h"
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/* Headers from readarchopenfpga library */
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#include "write_xml_utils.h"
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#include "write_xml_tile_annotation.h"
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/* namespace openfpga begins */
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namespace openfpga {
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/********************************************************************
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* A writer to output a device variation in a technology library to XML format
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*******************************************************************/
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static
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void write_xml_tile_annotation_global_port(std::fstream& fp,
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const char* fname,
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const openfpga::TileAnnotation& tile_annotation,
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const TileGlobalPortId& global_port_id) {
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/* Validate the file stream */
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openfpga::check_file_stream(fname, fp);
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fp << "\t\t" << "<global_port ";
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write_xml_attribute(fp, "name", tile_annotation.global_port_name(global_port_id).c_str());
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write_xml_attribute(fp, "is_clock", tile_annotation.global_port_is_clock(global_port_id));
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write_xml_attribute(fp, "is_set", tile_annotation.global_port_is_set(global_port_id));
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write_xml_attribute(fp, "is_reset", tile_annotation.global_port_is_reset(global_port_id));
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write_xml_attribute(fp, "default_value", tile_annotation.global_port_default_value(global_port_id));
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fp << ">" << "\n";
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for (size_t tile_info_id = 0; tile_info_id < tile_annotation.global_port_tile_names(global_port_id).size(); ++tile_info_id) {
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fp << "\t\t\t" << "<tile ";
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write_xml_attribute(fp, "name", tile_annotation.global_port_tile_names(global_port_id)[tile_info_id].c_str());
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write_xml_attribute(fp, "port", generate_xml_port_name(tile_annotation.global_port_tile_ports(global_port_id)[tile_info_id]).c_str());
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write_xml_attribute(fp, "x", tile_annotation.global_port_tile_coordinates(global_port_id)[tile_info_id].x());
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write_xml_attribute(fp, "y", tile_annotation.global_port_tile_coordinates(global_port_id)[tile_info_id].y());
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fp << "/>";
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}
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fp << "\t\t" << "</global_port>";
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}
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/********************************************************************
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* A writer to output tile annotations to XML format
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*******************************************************************/
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void write_xml_tile_annotations(std::fstream& fp,
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const char* fname,
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const TileAnnotation& tile_annotation) {
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/* Validate the file stream */
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openfpga::check_file_stream(fname, fp);
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/* Write the root node for pb_type annotations,
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* we apply a tab becuase pb_type annotations is just a subnode
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* under the root node <openfpga_arch>
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*/
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fp << "\t" << "<tile_annotations>" << "\n";
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/* Write device model one by one */
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for (const TileGlobalPortId& global_port_id : tile_annotation.global_ports()) {
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write_xml_tile_annotation_global_port(fp, fname, tile_annotation, global_port_id);
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}
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/* Write the root node for pb_type annotations */
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fp << "\t" << "</tile_annotations>" << "\n";
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}
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} /* namespace openfpga ends */
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