77 lines
3.1 KiB
C++
77 lines
3.1 KiB
C++
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/********************************************************************
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* This file include top-level function of FPGA-SPICE
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********************************************************************/
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/* Headers from vtrutil library */
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#include "vtr_log.h"
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#include "vtr_assert.h"
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#include "vtr_time.h"
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/* Headers from openfpgautil library */
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#include "openfpga_digest.h"
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#include "openfpga_reserved_words.h"
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#include "spice_constants.h"
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#include "spice_submodule.h"
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/* Header file for this source file */
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#include "spice_api.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* A top-level function of FPGA-SPICE which focuses on fabric Spice generation
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* This function will generate
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* - primitive modules required by the full fabric
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* - which are LUTs, routing multiplexer, logic gates, transmission-gates etc.
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* - Routing modules, which are Switch Blocks (SBs) and Connection Blocks (CBs)
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* - Logic block modules, which are Configuration Logic Blocks (CLBs)
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* - FPGA module, which are the full FPGA fabric with configuration protocol
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*
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* Note:
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* - Please do NOT include ANY testbench generation in this function!!!
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* It is about the fabric itself, independent from any implementation
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* All the testbench generation should be in the function fpga_testbench_spice()
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********************************************************************/
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void fpga_fabric_spice(const ModuleManager &module_manager,
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NetlistManager &netlist_manager,
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const FabricSpiceOption &options) {
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vtr::ScopedStartFinishTimer timer("Write SPICE netlists for FPGA fabric\n");
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std::string src_dir_path = format_dir_path(options.output_directory());
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/* Create directories */
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create_directory(src_dir_path);
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/* Sub directory under SRC directory to contain all the primitive block netlists */
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std::string submodule_dir_path = src_dir_path + std::string(DEFAULT_SUBMODULE_DIR_NAME);
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create_directory(submodule_dir_path);
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/* Sub directory under SRC directory to contain all the logic block netlists */
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std::string lb_dir_path = src_dir_path + std::string(DEFAULT_LB_DIR_NAME);
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create_directory(lb_dir_path);
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/* Sub directory under SRC directory to contain all the routing block netlists */
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std::string rr_dir_path = src_dir_path + std::string(DEFAULT_RR_DIR_NAME);
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create_directory(rr_dir_path);
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/* Generate primitive Spice modules, which are corner stones of FPGA fabric
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* Note that this function MUST be called before Spice generation of
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* core logic (i.e., logic blocks and routing resources) !!!
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* This is because that this function will add the primitive Spice modules to
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* the module manager.
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* Without the modules in the module manager, core logic generation is not possible!!!
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*/
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print_spice_submodule(netlist_manager,
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submodule_dir_path);
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/* Given a brief stats on how many Spice modules have been written to files */
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VTR_LOGV(options.verbose_output(),
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"Written %lu SPICE modules in total\n",
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module_manager.num_modules());
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}
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} /* end namespace openfpga */
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