44 lines
1.3 KiB
Coq
44 lines
1.3 KiB
Coq
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//-------------------------------------------
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// FPGA Synthesizable Verilog Netlist
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// Description: Wires
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// Author: Xifan TANG
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// Organization: EPFL/IC/LSI
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// Date: Thu Nov 15 14:26:09 2018
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//-------------------------------------------
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//----- Time scale -----
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`timescale 1ns / 1ps
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//-----Wire module, verilog_model_name=direct_interc -----
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module direct_interc (
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input wire in, output wire out);
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assign out = in;
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endmodule
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//-----END Wire module, verilog_model_name=direct_interc -----
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//----- Wire models for segments in routing -----
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//-----Wire module, verilog_model_name=chan_segment -----
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module chan_segment_seg0 (
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input wire in, output wire out, output wire mid_out);
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assign out = in;
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assign mid_out = in;
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endmodule
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//-----END Wire module, verilog_model_name=chan_segment -----
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//-----Wire module, verilog_model_name=chan_segment -----
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module chan_segment_seg1 (
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input wire in, output wire out, output wire mid_out);
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assign out = in;
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assign mid_out = in;
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endmodule
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//-----END Wire module, verilog_model_name=chan_segment -----
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//-----Wire module, verilog_model_name=chan_segment -----
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module chan_segment_seg2 (
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input wire in, output wire out, output wire mid_out);
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assign out = in;
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assign mid_out = in;
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endmodule
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//-----END Wire module, verilog_model_name=chan_segment -----
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