350 lines
20 KiB
XML
350 lines
20 KiB
XML
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<!-- An example architecture XML for OpenFPGA need
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Include three parts:
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1. simulation settings, where we define the options
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and process variations to be considered in simulations
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2. technology library, where we define transistor parameters
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in a vendor technology library
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3. circuit models, where we define circuit-level details for
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each primitives in FPGA architecture
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-->
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<openfpga_architecture>
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<technology_library>
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<device_library>
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<device_model name="logic" type="transistor">
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<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
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<design vdd="0.9" pn_ratio="2"/>
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<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
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<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
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</device_model>
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<device_model name="io" type="transistor">
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<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
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<design vdd="2.5" pn_ratio="3"/>
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<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
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<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
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</device_model>
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<device_model name="mem_rram" type="rram">
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<lib type="academia" ref="X" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/rram.pm"/>
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<rram rlrs="1e4" rhrs="1e5" variation="mem_rram_var"/>
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</device_model>
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<device_model name="logic_rram" type="rram">
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<lib type="academia" ref="X" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/rram.pm"/>
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<rram rlrs="5e3" rhrs="20e6" variation="logic_rram_var"/>
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</device_model>
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</device_library>
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<variation_library>
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<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
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<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
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<variation name="mem_rram_var" abs_deviation="0.1" num_sigma="3"/>
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<variation name="logic_rram_var" abs_deviation="0.1" num_sigma="3"/>
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</variation_library>
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</technology_library>
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<circuit_library>
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<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
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<design_technology type="cmos" topology="inverter" size="1"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
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<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
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<design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
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<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="input" prefix="sel" size="1"/>
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<port type="input" prefix="selb" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in sel selb" out_port="out">
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10e-12 5e-12 5e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in sel selb" out_port="out">
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10e-12 5e-12 5e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
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<design_technology type="cmos" topology="OR"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="a" size="1"/>
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<port type="input" prefix="b" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="a b" out_port="out">
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10e-12 10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="a b" out_port="out">
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10e-12 10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
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<design_technology type="cmos"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
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</circuit_model>
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<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
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<design_technology type="cmos"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
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</circuit_model>
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<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
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<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<!--mux2to1 subckt_name="mux2to1"/-->
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
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<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="tap_buf4"/>
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<!--mux2to1 subckt_name="mux2to1"/-->
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
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<design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="tap_buf4"/>
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<!--mux2to1 subckt_name="mux2to1"/-->
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
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<circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="D" size="1"/>
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<port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
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<port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
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</circuit_model>
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<circuit_model type="lut" name="lut5" prefix="lut5" dump_structural_verilog="true">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
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<lut_input_buffer exist="true" circuit_model_name="buf4"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="5"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="32"/>
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</circuit_model>
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<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
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<design_technology type="cmos" fracturable_lut="true"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
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<lut_input_buffer exist="true" circuit_model_name="buf4"/>
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<lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
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<port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3"/>
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<port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
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<port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
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<port type="sram" prefix="sram" size="64"/>
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<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
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</circuit_model>
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<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
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<design_technology type="cmos" fracturable_lut="true"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
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<lut_input_buffer exist="true" circuit_model_name="buf4"/>
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<lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="4" tri_state_map="--11" circuit_model_name="OR2"/>
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<port type="output" prefix="lut2_out" size="4" lut_frac_level="2" lut_output_mask="0,1,2,3"/>
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<port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
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<port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
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<port type="sram" prefix="sram" size="16"/>
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<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
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</circuit_model>
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<circuit_model type="sram" name="sram6T" prefix="sram" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/sram.v" >
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="2"/>
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</circuit_model>
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<circuit_model type="sram" name="sram6T_blwl" prefix="sram_blwl" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/sram.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="2"/>
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<port type="bl" prefix="bl" size="1" default_val="0" inv_circuit_model_name="INVTX1"/>
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<port type="blb" prefix="blb" size="1" default_val="1" inv_circuit_model_name="INVTX1"/>
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<port type="wl" prefix="wl" size="1" default_val="0" inv_circuit_model_name="INVTX1"/>
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</circuit_model>
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<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
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<circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="pReset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
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<port type="input" prefix="D" size="1"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="output" prefix="Qb" size="1"/>
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<port type="clock" prefix="prog_clk" size="1" is_global="true" default_val="0" is_prog="true"/>
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</circuit_model>
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<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="inout" prefix="pad" size="1"/>
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<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
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<port type="input" prefix="outpad" size="1"/>
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<port type="output" prefix="inpad" size="1"/>
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</circuit_model>
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<!-- Hard logic definition for heterogenous blocks -->
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<circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="a" size="1"/>
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<port type="input" prefix="b" size="1"/>
|
||
|
|
<port type="input" prefix="cin" size="1"/>
|
||
|
|
<port type="output" prefix="cout" size="1"/>
|
||
|
|
<port type="output" prefix="sumout" size="1"/>
|
||
|
|
</circuit_model>
|
||
|
|
</circuit_library>
|
||
|
|
<configuration_protocol>
|
||
|
|
<organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
|
||
|
|
</configuration_protocol>
|
||
|
|
<connection_block>
|
||
|
|
<switch name="cb_mux" circuit_model_name="mux_2level_tapbuf"/>
|
||
|
|
</connection_block>
|
||
|
|
<switch_block>
|
||
|
|
<switch name="sb_mux_L4" circuit_model_name="mux_2level_tapbuf"/>
|
||
|
|
</switch_block>
|
||
|
|
<routing_segment>
|
||
|
|
<segment name="L4" circuit_model_name="chan_segment"/>
|
||
|
|
</routing_segment>
|
||
|
|
<direct_connection>
|
||
|
|
<direct name="adder" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
|
||
|
|
</direct_connection>
|
||
|
|
<pb_type_annotations>
|
||
|
|
<!-- physical pb_type binding in complex block IO -->
|
||
|
|
<pb_type name="io" physical_mode_name="io_phy" idle_mode_name="inpad"/>
|
||
|
|
<pb_type name="io[io_phy].iopad" circuit_model_name="iopad" mode_bits="1"/>
|
||
|
|
<pb_type name="io[inpad].inpad" physical_pb_type_name="iopad" mode_bits="1"/>
|
||
|
|
<pb_type name="io[outpad].outpad" physical_pb_type_name="iopad" mode_bits="0"/>
|
||
|
|
<!-- End physical pb_type binding in complex block IO -->
|
||
|
|
|
||
|
|
<!-- physical pb_type binding in complex block CLB -->
|
||
|
|
<!-- physical mode will be the default mode if not specified -->
|
||
|
|
<pb_type name="clb">
|
||
|
|
<!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
|
||
|
|
<interconnect name="crossbar0" circuit_model_name="mux_2level"/>
|
||
|
|
<interconnect name="crossbar1" circuit_model_name="mux_2level"/>
|
||
|
|
<interconnect name="crossbar2" circuit_model_name="mux_2level"/>
|
||
|
|
<interconnect name="crossbar3" circuit_model_name="mux_2level"/>
|
||
|
|
<interconnect name="crossbar4" circuit_model_name="mux_2level"/>
|
||
|
|
<interconnect name="crossbar5" circuit_model_name="mux_2level"/>
|
||
|
|
</pb_type>
|
||
|
|
<pb_type name="clb.fle" physical_mode_name="fle_phy" idle_mode_name="n2_lut5"/>
|
||
|
|
<pb_type name="clb.fle[fle_phy].frac_logic.frac_lut6" mode_bits="11" circuit_model_name="frac_lut6"/>
|
||
|
|
<pb_type name="clb.fle[fle_phy].frac_logic.adder_phy" circuit_model_name="adder"/>
|
||
|
|
<pb_type name="clb.fle[fle_phy].frac_logic.ff_phy" circuit_model_name="static_dff"/>
|
||
|
|
<pb_type name="clb.fle[n2_lut5].lut5_inter.ble5[blut5].flut5.lut5" mode_bits="01" physical_pb_type_name="clb.fle[fle_phy].frac_logic.frac_lut6" physical_pb_type_index_factor="0.5">
|
||
|
|
<!-- If not specified, we by default assume the physical mode pin share the same name -->
|
||
|
|
<port name="in" physical_mode_port="in[4:0]"/>
|
||
|
|
<port name="out" physical_mode_port="lut5_out" physical_mode_pin_rotate_offset="1"/>
|
||
|
|
</pb_type>
|
||
|
|
<pb_type name="clb.fle[n2_lut5].lut5_inter.ble5[blut5].flut5.ff" physical_pb_type_name="clb.fle[fle_phy].frac_logic.ff_phy"/>
|
||
|
|
<pb_type name="clb.fle[n2_lut5].lut5_inter.ble5[arithmetic].arithemetic.lut4" mode_bits="11" physical_pb_type_name="clb.fle[fle_phy].frac_logic.frac_lut6">
|
||
|
|
<!-- If not specified, we by default assume the physical mode pin share the same name -->
|
||
|
|
<port name="in" physical_mode_port="in[3:0]"/>
|
||
|
|
<port name="out" physical_mode_port="lut4_out" physical_mode_pin_rotate_offset="1"/>
|
||
|
|
</pb_type>
|
||
|
|
<pb_type name="clb.fle[n2_lut5].lut5_inter.ble5[arithmetic].arithemetic.adder" physical_pb_type_name="clb.fle[fle_phy].frac_logic.adder_phy"/>
|
||
|
|
<pb_type name="clb.fle[n2_lut5].lut5_inter.ble5[arithmetic].arithemetic.ff" physical_pb_type_name="clb.fle[fle_phy].frac_logic.ff_phy"/>
|
||
|
|
<pb_type name="clb.fle[n1_lut6].ble6.lut6" mode_bits="00" physical_pb_type_name="clb.fle[fle_phy].frac_logic.frac_lut6">
|
||
|
|
<!-- If not specified, we by default assume the physical mode pin share the same name -->
|
||
|
|
<port name="in" physical_mode_port="in[5:0]"/>
|
||
|
|
<port name="out" physical_mode_port="lut6_out"/>
|
||
|
|
</pb_type>
|
||
|
|
<pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[fle_phy].frac_logic.ff_phy" physical_pb_type_index_factor="2" physical_pb_type_index_offset="1"/>
|
||
|
|
<pb_type name="clb.fle[shift_register].ble6_shift.ff" physical_pb_type_name="clb.fle[fle_phy].frac_logic.ff_phy"/>
|
||
|
|
<!-- End physical pb_type binding in complex block IO -->
|
||
|
|
</pb_type_annotations>
|
||
|
|
</openfpga_architecture>
|
||
|
|
<openfpga_simulation_setting>
|
||
|
|
<clock_setting>
|
||
|
|
<operating frequency="200e6" num_cycles="auto" slack="0.2"/>
|
||
|
|
<programming frequency="10e6"/>
|
||
|
|
</clock_setting>
|
||
|
|
<simulator_option>
|
||
|
|
<operating_condition temperature="25"/>
|
||
|
|
<output_log verbose="false" captab="false"/>
|
||
|
|
<accuracy type="abs" value="1e-13"/>
|
||
|
|
<runtime fast_simulation="true"/>
|
||
|
|
</simulator_option>
|
||
|
|
<monte_carlo num_simulation_points="2"/>
|
||
|
|
<measurement_setting>
|
||
|
|
<slew>
|
||
|
|
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
|
||
|
|
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
|
||
|
|
</slew>
|
||
|
|
<delay>
|
||
|
|
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
|
||
|
|
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
|
||
|
|
</delay>
|
||
|
|
</measurement_setting>
|
||
|
|
<stimulus>
|
||
|
|
<clock>
|
||
|
|
<rise slew_type="abs" slew_time="20e-12" />
|
||
|
|
<fall slew_type="abs" slew_time="20e-12" />
|
||
|
|
</clock>
|
||
|
|
<input>
|
||
|
|
<rise slew_type="abs" slew_time="25e-12" />
|
||
|
|
<fall slew_type="abs" slew_time="25e-12" />
|
||
|
|
</input>
|
||
|
|
</stimulus>
|
||
|
|
</openfpga_simulation_setting>
|