257 lines
6.9 KiB
C
257 lines
6.9 KiB
C
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#include <string.h>
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#include <assert.h>
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#include "util.h"
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#include "arch_types.h"
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#include "ReadLine.h"
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#include "ezxml.h"
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#include "read_xml_arch_file.h"
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#include "read_xml_util.h"
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/* mrFPGA */
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#include "read_xml_mrfpga.h"
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/* mrFPGA: reshaped by Xifan TANG*/
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void init_buffer_inf(t_buffer_inf* buffer_inf) {
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buffer_inf->C = 0.;
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buffer_inf->R = 0.;
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buffer_inf->Tdel = 0.;
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return;
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}
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void init_memristor_inf(t_memristor_inf* memristor_inf) {
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memristor_inf->C = 0.;
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memristor_inf->R = 0.;
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memristor_inf->Tdel = 0.;
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return;
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}
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/* Initial the mrfpga architecture */
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void init_arch_mrfpga(t_arch_mrfpga* arch_mrfpga) {
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/* Initial the booleans*/
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arch_mrfpga->is_isolation = FALSE;
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arch_mrfpga->is_stack = FALSE;
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arch_mrfpga->is_junction = FALSE;
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arch_mrfpga->is_wire_buffer = FALSE;
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arch_mrfpga->is_mrFPGA = FALSE;
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arch_mrfpga->is_accurate = FALSE;
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/*Initial some structs*/
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init_buffer_inf(&(arch_mrfpga->wire_buffer_inf));
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init_memristor_inf(&(arch_mrfpga->memristor_inf));
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/* Initial arch parameters*/
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arch_mrfpga->max_pins_per_side = 0;
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arch_mrfpga->main_best_buffer_list = NULL;
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arch_mrfpga->num_normal_switch = 0;
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arch_mrfpga->start_seg_switch = 0;
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/* RRAM and SRAM support*/
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arch_mrfpga->is_show_sram = FALSE;
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arch_mrfpga->is_show_pass_trans = FALSE;
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arch_mrfpga->tech_comp = CONV;
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arch_mrfpga->Rseg_global = 0.;
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arch_mrfpga->Cseg_global = 0.;
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arch_mrfpga->rram_pass_tran_value = 0.;
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arch_mrfpga->is_opin_cblock_defined = 0;
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return;
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}
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void
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ProcessTechHack(INOUTP ezxml_t Node,
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OUTP struct s_arch *arch) {
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const char *Prop;
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/* Xifan TANG: fill the struct mrfpga*/
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if ( Node ) {
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Prop = FindProperty(Node, "isolation", FALSE);
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if ( Prop ) {
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if ( strcmp(Prop,"no") == 0 ) {
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arch->arch_mrfpga.is_isolation = FALSE;
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}
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ezxml_set_attr(Node, "isolation", NULL);
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}
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Prop = FindProperty(Node, "stack", FALSE);
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if ( Prop ) {
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if ( strcmp(Prop,"no") == 0 ) {
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arch->arch_mrfpga.is_stack = FALSE;
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}
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ezxml_set_attr(Node, "stack", NULL);
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}
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Prop = FindProperty(Node, "junction", FALSE);
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if ( Prop ) {
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if ( strcmp(Prop,"no") == 0 ) {
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arch->arch_mrfpga.is_junction = FALSE;
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}
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ezxml_set_attr(Node, "junction", NULL);
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}
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}
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return;
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}
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void
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ProcessWireBuffer(INOUTP ezxml_t Node,
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OUTP struct s_arch *arch) {
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const char *Prop;
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if ( Node ) {
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/* is_wire_buffer*/
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arch->arch_mrfpga.is_wire_buffer = TRUE;
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/* Buffer resistance*/
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Prop = FindProperty(Node, "R", TRUE);
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arch->arch_mrfpga.wire_buffer_inf.R = atof(Prop);
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ezxml_set_attr(Node, "R", NULL);
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/* Buffer Cin*/
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Prop = FindProperty(Node, "Cin", TRUE);
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arch->arch_mrfpga.wire_buffer_inf.C = atof(Prop);
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ezxml_set_attr(Node, "Cin", NULL);
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/* TODO: (Xifan TANG) There should be a Cout for buffer ...*/
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ezxml_set_attr(Node, "Cout", NULL);
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/* Buffer Tdel */
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Prop = FindProperty(Node, "Tdel", TRUE);
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arch->arch_mrfpga.wire_buffer_inf.Tdel = atof(Prop);
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ezxml_set_attr(Node, "Tdel", NULL);
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}
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return;
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}
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static void
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ProcessTechComp(INOUTP ezxml_t Node,
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OUTP struct s_arch *arch) {
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const char *Prop;
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/*
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Prop = FindProperty(Node, "paper", FALSE);
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if (Prop != NULL) {
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if (strcmp(Prop,"mono")==0) {
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arch->arch_mrfpga.tech_comp = MONO;
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} else if (strcmp(Prop,"sttram")==0) {
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arch->arch_mrfpga.tech_comp = STTRAM;
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} else if (strcmp(Prop,"pcram_xie")==0) {
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arch->arch_mrfpga.tech_comp = PCRAM_Xie;
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}else if (strcmp(Prop,"pcram_pierre")==0) {
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arch->arch_mrfpga.tech_comp = PCRAM_Pierre;
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} else if(strcmp(Prop,"nem")==0) {
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arch->arch_mrfpga.tech_comp = NEM;
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} else {
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printf("Unknown property %s for tech_comp value\n", Prop);
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exit(1);
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}
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ezxml_set_attr(Node, "paper", NULL);
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}
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*/
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Prop = FindProperty(Node, "rram_pass_tran_value", FALSE);
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if(Prop != NULL) {
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arch->arch_mrfpga.rram_pass_tran_value = atof(Prop);
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ezxml_set_attr(Node, "rram_pass_tran_value", NULL);
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}
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return;
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}
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void
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ProcessmrFPGA(INOUTP ezxml_t Node,
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OUTP struct s_arch *arch) {
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const char *Prop;
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ezxml_t Cur;
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arch->arch_mrfpga.is_isolation = TRUE;
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arch->arch_mrfpga.is_junction = TRUE;
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arch->arch_mrfpga.is_stack = TRUE;
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/* Xifan TANG: Abolish hack */
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/*
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Cur = FindElement(Node, "hack", FALSE);
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ProcessTechHack(Cur,arch);
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*/
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if (arch->arch_mrfpga.is_isolation && arch->arch_mrfpga.is_junction && arch->arch_mrfpga.is_stack) {
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arch->arch_mrfpga.is_mrFPGA = TRUE;
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} else {
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arch->arch_mrfpga.is_mrFPGA = FALSE;
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}
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if(arch->arch_mrfpga.is_junction) {
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/* Read Resistance */
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Prop = FindProperty(Node, "R", TRUE);
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arch->arch_mrfpga.memristor_inf.R = atof(Prop);
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ezxml_set_attr(Node, "R", NULL);
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/* Read Capacitance */
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Prop = FindProperty(Node, "C", TRUE);
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arch->arch_mrfpga.memristor_inf.C = atof(Prop);
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ezxml_set_attr(Node, "C", NULL);
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/* Read instrinsic delay*/
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Prop = FindProperty(Node, "Tdel", TRUE);
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arch->arch_mrfpga.memristor_inf.Tdel = atof(Prop);
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ezxml_set_attr(Node, "Tdel", NULL);
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}
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/* buffer */
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Cur = FindElement(Node, "buffer", FALSE);
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ProcessWireBuffer(Cur,arch);
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if(Cur) {
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FreeNode(Cur);
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}
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/* buffer */
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Cur = FindElement(Node, "cblock", FALSE);
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ProcessMrFPGATiming(Cur,arch);
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if(Cur) {
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FreeNode(Cur);
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}
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return;
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}
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void
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ProcessTechnology(INOUTP ezxml_t Node,
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OUTP struct s_arch *arch) {
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ezxml_t Cur;
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/* mrFPGA: Xifan TANG
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* I move the globals into a struct so that
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* we can use static library link
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*/
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init_arch_mrfpga(&(arch->arch_mrfpga));
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if ( Node ) {
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Cur = FindElement(Node, "mrFPGA", FALSE);
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if ( Cur ) {
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ProcessmrFPGA(Cur, arch);
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FreeNode(Cur);
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}
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Cur = FindElement(Node, "tech_comp", FALSE);
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if ( Cur ) {
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ProcessTechComp(Cur, arch);
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FreeNode(Cur);
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}
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}
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return;
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}
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/* Xifan TANG: mrFPGA has a child called timing, define the R_opin_cblock and T_opin_cblock */
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void ProcessMrFPGATiming(INOUTP ezxml_t Cur,
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OUTP t_arch* arch) {
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const char *Prop = NULL;
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if(Cur != NULL) {
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/* set the defined flag*/
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arch->arch_mrfpga.is_opin_cblock_defined = 1;
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Prop = FindProperty(Cur, "R_opin_cblock", TRUE);
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arch->arch_mrfpga.R_opin_cblock = atof(Prop);
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ezxml_set_attr(Cur, "R_opin_cblock", NULL);
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Prop = FindProperty(Cur, "T_opin_cblock", TRUE);
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arch->arch_mrfpga.T_opin_cblock = atof(Prop);
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ezxml_set_attr(Cur, "T_opin_cblock", NULL);
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}
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return;
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}
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/* end */
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