202 lines
7.4 KiB
Coq
202 lines
7.4 KiB
Coq
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Zig-Zag Unit ////
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//// Performs zigzag-ing, as used by many DCT based encoders ////
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//// ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2002 Richard Herveille ////
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//// richard@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: zigzag.v,v 1.2 2002-10-23 09:06:59 rherveille Exp $
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//
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// $Date: 2002-10-23 09:06:59 $
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// $Revision: 1.2 $
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// $Author: rherveille $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: not supported by cvs2svn $
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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module zigzag(
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clk,
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ena,
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dstrb,
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din_00, din_01, din_02, din_03, din_04, din_05, din_06, din_07,
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din_10, din_11, din_12, din_13, din_14, din_15, din_16, din_17,
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din_20, din_21, din_22, din_23, din_24, din_25, din_26, din_27,
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din_30, din_31, din_32, din_33, din_34, din_35, din_36, din_37,
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din_40, din_41, din_42, din_43, din_44, din_45, din_46, din_47,
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din_50, din_51, din_52, din_53, din_54, din_55, din_56, din_57,
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din_60, din_61, din_62, din_63, din_64, din_65, din_66, din_67,
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din_70, din_71, din_72, din_73, din_74, din_75, din_76, din_77,
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dout,
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douten
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);
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//
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// inputs & outputs
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//
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input clk; // system clock
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input ena; // clock enable
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input dstrb; // data-strobe. Present dstrb 1clk-cycle before data block
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input [11:0]
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din_00, din_01, din_02, din_03, din_04, din_05, din_06, din_07,
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din_10, din_11, din_12, din_13, din_14, din_15, din_16, din_17,
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din_20, din_21, din_22, din_23, din_24, din_25, din_26, din_27,
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din_30, din_31, din_32, din_33, din_34, din_35, din_36, din_37,
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din_40, din_41, din_42, din_43, din_44, din_45, din_46, din_47,
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din_50, din_51, din_52, din_53, din_54, din_55, din_56, din_57,
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din_60, din_61, din_62, din_63, din_64, din_65, din_66, din_67,
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din_70, din_71, din_72, din_73, din_74, din_75, din_76, din_77;
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output [11:0] dout;
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output douten; // data-out enable
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//
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// variables
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//
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reg ld_zigzag;
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reg [11:0] sresult [63:0]; // store results for zig-zagging
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//
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// module body
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//
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always @(posedge clk)
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if(ena)
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ld_zigzag <= #1 dstrb;
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assign douten = ld_zigzag;
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//
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// Generate zig-zag structure
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//
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// This implicates that the quantization step be performed after
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// the zig-zagging.
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//
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// 0: 1: 2: 3: 4: 5: 6: 7: 0: 1: 2: 3: 4: 5: 6: 7:
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// 0: 63 62 58 57 49 48 36 35 3f 3e 3a 39 31 30 24 23
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// 1: 61 59 56 50 47 37 34 21 3d 3b 38 32 2f 25 22 15
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// 2: 60 55 51 46 38 33 22 20 3c 37 33 2e 26 21 16 14
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// 3: 54 52 45 39 32 23 19 10 36 34 2d 27 20 17 13 0a
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// 4: 53 44 40 31 24 18 11 09 35 2c 28 1f 18 12 0b 09
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// 5: 43 41 30 25 17 12 08 03 2b 29 1e 19 11 0c 08 03
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// 6: 42 29 26 16 13 07 04 02 2a 1d 1a 10 0d 07 04 02
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// 7: 28 27 15 14 06 05 01 00 1c 1b 0f 0e 06 05 01 00
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//
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// zig-zag the DCT results
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integer n;
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always @(posedge clk)
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if(ena)
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if(ld_zigzag) // reload results-register file
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begin
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sresult[63] <= #1 din_00;
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sresult[62] <= #1 din_01;
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sresult[61] <= #1 din_10;
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sresult[60] <= #1 din_20;
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sresult[59] <= #1 din_11;
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sresult[58] <= #1 din_02;
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sresult[57] <= #1 din_03;
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sresult[56] <= #1 din_12;
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sresult[55] <= #1 din_21;
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sresult[54] <= #1 din_30;
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sresult[53] <= #1 din_40;
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sresult[52] <= #1 din_31;
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sresult[51] <= #1 din_22;
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sresult[50] <= #1 din_13;
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sresult[49] <= #1 din_04;
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sresult[48] <= #1 din_05;
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sresult[47] <= #1 din_14;
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sresult[46] <= #1 din_23;
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sresult[45] <= #1 din_32;
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sresult[44] <= #1 din_41;
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sresult[43] <= #1 din_50;
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sresult[42] <= #1 din_60;
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sresult[41] <= #1 din_51;
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sresult[40] <= #1 din_42;
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sresult[39] <= #1 din_33;
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sresult[38] <= #1 din_24;
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sresult[37] <= #1 din_15;
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sresult[36] <= #1 din_06;
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sresult[35] <= #1 din_07;
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sresult[34] <= #1 din_16;
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sresult[33] <= #1 din_25;
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sresult[32] <= #1 din_34;
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sresult[31] <= #1 din_43;
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sresult[30] <= #1 din_52;
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sresult[29] <= #1 din_61;
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sresult[28] <= #1 din_70;
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sresult[27] <= #1 din_71;
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sresult[26] <= #1 din_62;
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sresult[25] <= #1 din_53;
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sresult[24] <= #1 din_44;
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sresult[23] <= #1 din_35;
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sresult[22] <= #1 din_26;
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sresult[21] <= #1 din_17;
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sresult[20] <= #1 din_27;
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sresult[19] <= #1 din_36;
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sresult[18] <= #1 din_45;
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sresult[17] <= #1 din_54;
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sresult[16] <= #1 din_63;
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sresult[15] <= #1 din_72;
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sresult[14] <= #1 din_73;
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sresult[13] <= #1 din_64;
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sresult[12] <= #1 din_55;
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sresult[11] <= #1 din_46;
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sresult[10] <= #1 din_37;
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sresult[09] <= #1 din_47;
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sresult[08] <= #1 din_56;
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sresult[07] <= #1 din_65;
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sresult[06] <= #1 din_74;
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sresult[05] <= #1 din_75;
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sresult[04] <= #1 din_66;
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sresult[03] <= #1 din_57;
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sresult[02] <= #1 din_67;
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sresult[01] <= #1 din_76;
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sresult[00] <= #1 din_77;
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end
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else // shift results out
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for (n=1; n<=63; n=n+1) // do not change sresult[0]
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sresult[n] <= #1 sresult[n -1];
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assign dout = sresult[63];
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endmodule
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