2020-11-10 15:32:24 -06:00
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/********************************************************************
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* This file includes the top-level function of this library
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* which reads an XML modeling OpenFPGA architecture to the associated
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* data structures
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*******************************************************************/
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#include <string>
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/* Headers from pugi XML library */
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#include "pugixml.hpp"
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#include "pugixml_util.hpp"
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/* Headers from vtr util library */
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#include "vtr_assert.h"
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/* Headers from libarchfpga */
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#include "arch_error.h"
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#include "read_xml_util.h"
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/* Headers from libopenfpgautil */
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#include "openfpga_tokenizer.h"
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#include "openfpga_port_parser.h"
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#include "read_xml_tile_annotation.h"
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/********************************************************************
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* Parse XML description for an interconnection annotation
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* under a <global_port> XML node
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*******************************************************************/
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static
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void read_xml_tile_global_port_annotation(pugi::xml_node& xml_tile,
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const pugiutil::loc_data& loc_data,
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openfpga::TileAnnotation& tile_annotation) {
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2021-01-09 19:47:12 -06:00
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/* We have mandatory XML attributes:
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* - name of the port
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2020-11-10 15:32:24 -06:00
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*/
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const std::string& name_attr = get_attribute(xml_tile, "name", loc_data).as_string();
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2021-01-09 19:47:12 -06:00
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TileGlobalPortId tile_global_port_id = tile_annotation.create_global_port(name_attr);
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2020-11-10 15:32:24 -06:00
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2020-11-11 14:59:24 -06:00
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/* Report any duplicated port names */
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if (TileGlobalPortId::INVALID() == tile_global_port_id) {
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archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_tile),
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"Invalid port name '%s' which is defined more than once in the global port list!\n",
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name_attr.c_str());
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}
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2021-01-09 19:47:12 -06:00
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/* Iterate over the children under this node,
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* each child should be named after <pb_type>
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*/
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for (pugi::xml_node xml_tile_port : xml_tile.children()) {
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/* Error out if the XML child has an invalid name! */
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if (xml_tile_port.name() != std::string("tile")) {
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bad_tag(xml_tile_port, loc_data, xml_tile, {"tile"});
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}
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/* Parse the name of the tiles and ports */
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const std::string& tile_name_attr = get_attribute(xml_tile_port, "name", loc_data).as_string();
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const std::string& port_name_attr = get_attribute(xml_tile_port, "port", loc_data).as_string();
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/* Extract the tile port information */
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openfpga::PortParser tile_port_parser(port_name_attr);
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/* Parse tile coordinates */
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2021-01-09 19:56:41 -06:00
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vtr::Point<size_t> tile_coord(get_attribute(xml_tile_port, "x", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(-1),
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get_attribute(xml_tile_port, "y", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(-1));
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2021-01-09 19:47:12 -06:00
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/* Add tile port information */
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tile_annotation.add_global_port_tile_information(tile_global_port_id,
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tile_name_attr,
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tile_port_parser.port(),
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tile_coord);
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}
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/* Check: Must have at least one global port tile information */
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if (true == tile_annotation.global_port_tile_names(tile_global_port_id).empty()) {
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archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_tile),
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"Invalid tile annotation for global port '%s'! At least 1 tile port definition is expected!\n",
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name_attr.c_str());
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}
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2020-11-10 15:32:24 -06:00
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/* Get is_clock attributes */
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2020-11-10 21:31:14 -06:00
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tile_annotation.set_global_port_is_clock(tile_global_port_id, get_attribute(xml_tile, "is_clock", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
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2020-11-10 15:32:24 -06:00
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/* Get is_set attributes */
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2020-11-10 21:31:14 -06:00
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tile_annotation.set_global_port_is_set(tile_global_port_id, get_attribute(xml_tile, "is_set", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
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2020-11-10 15:32:24 -06:00
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/* Get is_reset attributes */
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2020-11-10 21:31:14 -06:00
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tile_annotation.set_global_port_is_reset(tile_global_port_id, get_attribute(xml_tile, "is_reset", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
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2020-11-10 15:32:24 -06:00
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/* Get default_value attributes */
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2020-12-02 18:03:48 -06:00
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tile_annotation.set_global_port_default_value(tile_global_port_id, get_attribute(xml_tile, "default_val", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(0));
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2020-11-11 14:59:24 -06:00
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/* Ensure valid port attributes */
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if (false == tile_annotation.valid_global_port_attributes(tile_global_port_id)) {
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archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_tile),
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"Invalid port attributes for '%s'! A port can only be clock or set or reset.\n",
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name_attr.c_str());
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}
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2020-11-10 15:32:24 -06:00
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}
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/********************************************************************
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* Top function to parse XML description about tile annotation
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*******************************************************************/
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openfpga::TileAnnotation read_xml_tile_annotations(pugi::xml_node& Node,
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const pugiutil::loc_data& loc_data) {
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2020-11-10 15:32:24 -06:00
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openfpga::TileAnnotation tile_annotations;
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/* Parse configuration protocol root node */
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pugi::xml_node xml_annotations = get_single_child(Node, "tile_annotations", loc_data, pugiutil::ReqOpt::OPTIONAL);
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/* Not found, we can return */
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if (!xml_annotations) {
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return tile_annotations;
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}
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/* Iterate over the children under this node,
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* each child should be named after <pb_type>
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*/
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for (pugi::xml_node xml_tile_global_port : xml_annotations.children()) {
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/* Error out if the XML child has an invalid name! */
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if (xml_tile_global_port.name() != std::string("global_port")) {
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bad_tag(xml_tile_global_port, loc_data, xml_annotations, {"global_port"});
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}
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read_xml_tile_global_port_annotation(xml_tile_global_port, loc_data, tile_annotations);
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}
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return tile_annotations;
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}
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