27 lines
1.4 KiB
Markdown
27 lines
1.4 KiB
Markdown
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To compile the following testbenches :
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- You need to add both testbench & sva_checker to your project.
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- You can enable/disable the checker by changing the "enable_assertions" parameter in the testbench
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bind fpga_top inv_checker #(.enable_assertions(1)) when you need to enable assertions
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bind fpga_top inv_checker #(.enable_assertions(0)) when you need to disable assertions
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Disabling assertions for the current architecture saves about 3% simulation runtime.
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- The checker is tuned for 4clb with 20FF each 2x2, bitstream lenght & number of flipflop is set by default for this specific architecture but it can be modified through BS_LGT & FF_N parameter inside the testbench.
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Descriptions of features being checked are written in the verification_plan.ods file in this directory.
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Testbench should always raise a simulation succeed flag but when an error is being detected, sva_checker module will stop the simulation and write an error message.
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You can turn that error message to a warning message which will not stop the simulation by modifiying the following line in sva_checker.sv :
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`define assert_prog_clk( arg ) \
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assert property (@(posedge prog_clk) disable iff (pReset || (enable_assertions == 1'b0)) arg ) else $error("Simulation failed");
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becomes
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`define assert_prog_clk( arg ) \
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assert property (@(posedge prog_clk) disable iff (pReset || (enable_assertions == 1'b0)) arg ) else $warning("Simulation failed");
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