81 lines
4.3 KiB
Coq
81 lines
4.3 KiB
Coq
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name "bus_commands.v" ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// Author(s): ////
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//// - Miha Dolenc (mihad@opencores.org) ////
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//// ////
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//// All additional information is avaliable in the README.pdf ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: bus_commands.v,v $
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// Revision 1.4 2002/08/22 13:28:05 mihad
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// Updated for synthesis purposes. Gate level simulation was failing in some configurations
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//
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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// Revision 1.2 2001/10/05 08:14:28 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// New project directory structure
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//
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//
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// definitions of PCI bus commands | used by PCI Master | used by PCI Target
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`define BC_IACK 4'h0 // yes no
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`define BC_SPECIAL 4'h1 // no no
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`define BC_IO_READ 4'h2 // yes yes
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`define BC_IO_WRITE 4'h3 // yes yes
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`define BC_RESERVED0 4'h4 // no no
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`define BC_RESERVED1 4'h5 // no no
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`define BC_MEM_READ 4'h6 // yes yes
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`define BC_MEM_WRITE 4'h7 // yes yes
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`define BC_RESERVED2 4'h8 // no no
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`define BC_RESERVED3 4'h9 // no no
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`define BC_CONF_READ 4'hA // yes yes
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`define BC_CONF_WRITE 4'hB // yes yes
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`define BC_MEM_READ_MUL 4'hC // yes yes
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`define BC_DUAL_ADDR_CYC 4'hD // no no
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`define BC_MEM_READ_LN 4'hE // yes yes
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`define BC_MEM_WRITE_INVAL 4'hF // no yes
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// common bits for configuration cycle commands
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`define BC_CONF_RW 3'b101
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// common bits for io cycle commands
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`define BC_IO_RW 3'b001
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