57 lines
1.4 KiB
Plaintext
57 lines
1.4 KiB
Plaintext
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read_verilog -specify specify.v
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prep
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cd test
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select t:$specify2 -assert-count 0
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select t:$specify3 -assert-count 1
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select t:$specrule -assert-count 2
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cd test2
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select t:$specify2 -assert-count 2
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select t:$specify3 -assert-count 0
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select t:$specrule -assert-count 0
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cd
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write_verilog specify.out
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design -stash gold
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read_verilog -specify specify.out
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prep
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cd test
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select t:$specify2 -assert-count 0
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select t:$specify3 -assert-count 1
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select t:$specrule -assert-count 2
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cd test2
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select t:$specify2 -assert-count 2
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select t:$specify3 -assert-count 0
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select t:$specrule -assert-count 0
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cd
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design -stash gate
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design -copy-from gold -as gold test
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design -copy-from gate -as gate test
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rename -hide
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rename -enumerate -pattern A_% t:$specify3
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rename -enumerate -pattern B_% t:$specrule r:TYPE=$setup %i
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rename -enumerate -pattern C_% t:$specrule r:TYPE=$hold %i
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select n:A_* -assert-count 2
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select n:B_* -assert-count 2
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select n:C_* -assert-count 2
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equiv_make gold gate equiv
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hierarchy -top equiv
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equiv_struct
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equiv_induct -seq 5
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equiv_status -assert
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design -reset
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design -copy-from gold -as gold test2
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design -copy-from gate -as gate test2
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rename -hide
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rename -enumerate -pattern A_% t:$specify2 r:T_RISE_TYP=1 %i
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rename -enumerate -pattern B_% t:$specify2 n:A_* %d
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select n:A_* -assert-count 2
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select n:B_* -assert-count 2
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equiv_make gold gate equiv
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hierarchy -top equiv
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equiv_struct
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equiv_induct -seq 5
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equiv_status -assert
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design -reset
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