OpenFPGA/libopenfpga/libarchopenfpga/arch/sample_arch.xml

<!-- An example architecture XML for OpenFPGA need
     Include three parts:
     1. simulation settings, where we define the options 
        and process variations to be considered in simulations
     2. technology library, where we define transistor parameters
        in a vendor technology library
     3. circuit models, where we define circuit-level details for
        each primitives in FPGA architecture
  -->
<openfpga_architecture>
  <technology>
    <library lib_type="academia" transistor_type="TOP_TT" lib_path="OPENFPGAPATHKEYWORD/fpga_flow/tech/PTM_45nm/45nm.pm" nominal_vdd="1.0" io_vdd="2.5"/>
    <transistors pn_ratio="2" model_ref="M">
      <nmos model_name="nch" chan_length="40e-9" min_width="140e-9"/>
      <pmos model_name="pch" chan_length="40e-9" min_width="140e-9"/>
      <io_nmos model_name="nch_25" chan_length="270e-9" min_width="320e-9"/>
      <io_pmos model_name="pch_25" chan_length="270e-9" min_width="320e-9"/>
    </transistors>
    <rram model_name="rram" rlrs="5e3" rhrs="20e6"/> 
  </technology>
  <circuit_library>
    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
      <design_technology type="cmos" topology="inverter" size="1"/>
      <port type="input" prefix="in" size="1"/>
      <port type="output" prefix="out" size="1"/>
      <delay_matrix type="rise" in_port="in" out_port="out">
        10e-12
      </delay_matrix>
      <delay_matrix type="fall" in_port="in" out_port="out">
        10e-12
      </delay_matrix>
    </circuit_model>
    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
      <port type="input" prefix="in" size="1"/>
      <port type="output" prefix="out" size="1"/>
      <delay_matrix type="rise" in_port="in" out_port="out">
        10e-12
      </delay_matrix>
      <delay_matrix type="fall" in_port="in" out_port="out">
        10e-12
      </delay_matrix>
    </circuit_model>
    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
      <port type="input" prefix="in" size="1"/>
      <port type="output" prefix="out" size="1"/>
      <delay_matrix type="rise" in_port="in" out_port="out">
        10e-12
      </delay_matrix>
      <delay_matrix type="fall" in_port="in" out_port="out">
        10e-12
      </delay_matrix>
    </circuit_model>
    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
      <input_buffer exist="false"/>
      <output_buffer exist="false"/>
      <port type="input" prefix="in" size="1"/>
      <port type="input" prefix="sel" size="1"/>
      <port type="input" prefix="selb" size="1"/>
      <port type="output" prefix="out" size="1"/>
      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
        10e-12 5e-12 5e-12
      </delay_matrix>
      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
        10e-12 5e-12 5e-12
      </delay_matrix>
    </circuit_model>
    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
      <design_technology type="cmos" topology="OR"/>
      <input_buffer exist="false"/>
      <output_buffer exist="false"/>
      <port type="input" prefix="a" size="1"/>
      <port type="input" prefix="b" size="1"/>
      <port type="output" prefix="out" size="1"/>
      <delay_matrix type="rise" in_port="a b" out_port="out">
        10e-12 10e-12
      </delay_matrix>
      <delay_matrix type="fall" in_port="a b" out_port="out">
        10e-12 10e-12
      </delay_matrix>
    </circuit_model>
    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
      <design_technology type="cmos"/>
      <input_buffer exist="false"/>
      <output_buffer exist="false"/>
      <port type="input" prefix="in" size="1"/>
      <port type="output" prefix="out" size="1"/>
      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
    </circuit_model>
    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
      <design_technology type="cmos"/>
      <input_buffer exist="false"/>
      <output_buffer exist="false"/>
      <port type="input" prefix="in" size="1"/>
      <port type="output" prefix="out" size="1"/>
      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
    </circuit_model>
    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
      <input_buffer exist="true" circuit_model_name="INVTX1"/>
      <output_buffer exist="true" circuit_model_name="INVTX1"/>
      <!--mux2to1 subckt_name="mux2to1"/-->
      <pass_gate_logic circuit_model_name="TGATE"/>
      <port type="input" prefix="in" size="1"/>
      <port type="output" prefix="out" size="1"/>
      <port type="sram" prefix="sram" size="1"/>
    </circuit_model>
    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
      <input_buffer exist="true" circuit_model_name="INVTX1"/>
      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
      <!--mux2to1 subckt_name="mux2to1"/-->
      <pass_gate_logic circuit_model_name="TGATE"/>
      <port type="input" prefix="in" size="1"/>
      <port type="output" prefix="out" size="1"/>
      <port type="sram" prefix="sram" size="1"/>
    </circuit_model>
    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
      <input_buffer exist="true" circuit_model_name="INVTX1"/>
      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
      <!--mux2to1 subckt_name="mux2to1"/-->
      <pass_gate_logic circuit_model_name="TGATE"/>
      <port type="input" prefix="in" size="1"/>
      <port type="output" prefix="out" size="1"/>
      <port type="sram" prefix="sram" size="1"/>
    </circuit_model>
    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="D" size="1"/>
       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
       <port type="output" prefix="Q" size="1"/>
       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
    </circuit_model>
    <circuit_model type="lut" name="lut5" prefix="lut5" dump_structural_verilog="true">
      <design_technology type="cmos"/>
      <input_buffer exist="true" circuit_model_name="INVTX1"/>
      <output_buffer exist="true" circuit_model_name="INVTX1"/>
      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
      <pass_gate_logic circuit_model_name="TGATE"/>
      <port type="input" prefix="in" size="5"/>
      <port type="output" prefix="out" size="1"/>
      <port type="sram" prefix="sram" size="32"/>
    </circuit_model>
    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
      <design_technology type="cmos" fracturable_lut="true"/>
      <input_buffer exist="true" circuit_model_name="INVTX1"/>
      <output_buffer exist="true" circuit_model_name="INVTX1"/>
      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
  	  <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
      <pass_gate_logic circuit_model_name="TGATE"/>
      <port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
      <port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3"/>
      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
      <port type="sram" prefix="sram" size="64"/>
      <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
    </circuit_model>
    <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
      <design_technology type="cmos" fracturable_lut="true"/>
      <input_buffer exist="true" circuit_model_name="INVTX1"/>
      <output_buffer exist="true" circuit_model_name="INVTX1"/>
      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
  	  <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-"/>
      <pass_gate_logic circuit_model_name="TGATE"/>
      <port type="input" prefix="in" size="4" tri_state_map="--11" circuit_model_name="OR2"/>
      <port type="output" prefix="lut2_out" size="4" lut_frac_level="2" lut_output_mask="0,1,2,3"/>
      <port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
      <port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
      <port type="sram" prefix="sram" size="16"/>
      <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
    </circuit_model>
    <circuit_model type="sram" name="sram6T" prefix="sram" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/sram.v" >
      <design_technology type="cmos"/>
      <input_buffer exist="true" circuit_model_name="INVTX1"/>
      <output_buffer exist="true" circuit_model_name="INVTX1"/>
      <pass_gate_logic circuit_model_name="TGATE"/>
      <port type="input" prefix="in" size="1"/>
      <port type="output" prefix="out" size="2"/>
    </circuit_model>
    <circuit_model type="sram" name="sram6T_blwl" prefix="sram_blwl" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/sram.v">
      <design_technology type="cmos"/>
      <input_buffer exist="true" circuit_model_name="INVTX1"/>
      <output_buffer exist="true" circuit_model_name="INVTX1"/>
      <pass_gate_logic circuit_model_name="TGATE"/>
      <port type="input" prefix="in" size="1"/>
      <port type="output" prefix="out" size="2"/>
      <port type="bl" prefix="bl" size="1" default_val="0" inv_circuit_model_name="INVTX1"/>
      <port type="blb" prefix="blb" size="1" default_val="1" inv_circuit_model_name="INVTX1"/>
      <port type="wl" prefix="wl" size="1" default_val="0" inv_circuit_model_name="INVTX1"/>
    </circuit_model>
    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="pReset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
       <port type="input" prefix="D" size="1"/>
       <port type="output" prefix="Q" size="1"/>
       <port type="output" prefix="Qb" size="1"/>
       <port type="clock" prefix="prog_clk" size="1" is_global="true" default_val="0" is_prog="true"/>
    </circuit_model>
    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
      <design_technology type="cmos"/>
      <input_buffer exist="true" circuit_model_name="INVTX1"/>
      <output_buffer exist="true" circuit_model_name="INVTX1"/>
      <pass_gate_logic circuit_model_name="TGATE"/>
      <port type="inout" prefix="pad" size="1"/>
      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
      <port type="input" prefix="outpad" size="1"/>
      <port type="output" prefix="inpad" size="1"/>
    </circuit_model>
    <!-- Hard logic definition for heterogenous blocks -->
    <circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
       <port type="input" prefix="a" size="1"/>
       <port type="input" prefix="b" size="1"/>
       <port type="input" prefix="cin" size="1"/>
       <port type="output" prefix="cout" size="1"/>
       <port type="output" prefix="sumout" size="1"/>
    </circuit_model>
  </circuit_library>
</openfpga_architecture>
<openfpga_verification>
  <simulation_parameters>
    <options sim_temp="25" post="off" captab="off" fast="on"/>
    <monte_carlo mc_sim="off" num_mc_points="2" cmos_variation="off" rram_variation="off">
      <cmos abs_variation="0.1" num_sigma="3"/>
      <rram abs_variation="0.1" num_sigma="3"/>
    </monte_carlo>
    <measure sim_num_clock_cycle="auto" accuracy="1e-13" accuracy_type="abs">
      <slew>
        <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
        <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
      </slew>
      <delay>
        <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
        <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
      </delay>
    </measure>
    <stimuli>
      <clock op_freq="200e6" sim_slack="0.2" prog_freq="10e6">
        <rise slew_time="20e-12" slew_type="abs"/>
        <fall slew_time="20e-12" slew_type="abs"/>
      </clock>
      <input>
        <rise slew_time="25e-12" slew_type="abs"/>
        <fall slew_time="25e-12" slew_type="abs"/>
      </input>
    </stimuli>
  </simulation_parameters>
</openfpga_verification>