2020-07-04 18:31:34 -05:00
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#!/bin/bash
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set -e
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start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
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cd ${TRAVIS_BUILD_DIR}
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###############################################
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# OpenFPGA Shell with VPR8
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##############################################
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echo -e "Basic regression tests";
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echo -e "Testing configuration chain of a K4N4 FPGA";
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2020-07-04 20:06:41 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py full_testbench/configuration_chain --debug --show_thread_logs
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2020-07-15 12:57:12 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py full_testbench/fast_configuration_chain --debug --show_thread_logs
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2020-07-04 20:06:41 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py preconfig_testbench/configuration_chain --debug --show_thread_logs
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2020-07-04 18:31:34 -05:00
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echo -e "Testing fram-based configuration protocol of a K4N4 FPGA";
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2020-07-04 20:06:41 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py full_testbench/configuration_frame --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py full_testbench/fast_configuration_frame --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py preconfig_testbench/configuration_frame --debug --show_thread_logs
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2020-07-04 18:31:34 -05:00
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echo -e "Testing memory bank configuration protocol of a K4N4 FPGA";
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2020-07-04 20:06:41 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py full_testbench/memory_bank --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py full_testbench/fast_memory_bank --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py preconfig_testbench/memory_bank --debug --show_thread_logs
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2020-07-04 18:31:34 -05:00
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echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FPGA";
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2020-07-04 20:06:41 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py full_testbench/flatten_memory --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py preconfig_testbench/flatten_memory --debug --show_thread_logs
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2020-07-04 18:31:34 -05:00
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echo -e "Testing fabric Verilog generation only";
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2020-07-04 20:06:41 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py generate_fabric --debug --show_thread_logs
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2020-07-04 18:31:34 -05:00
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echo -e "Testing Verilog testbench generation only";
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2020-07-04 20:06:41 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py generate_testbench --debug --show_thread_logs
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2020-07-04 18:31:34 -05:00
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echo -e "Testing user-defined simulation settings: clock frequency and number of cycles";
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2020-07-04 20:06:41 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py fixed_simulation_settings --debug --show_thread_logs
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2020-07-04 18:31:34 -05:00
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end_section "OpenFPGA.TaskTun"
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