2020-01-30 22:39:44 -06:00
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# Run VPR for the s298 design
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2020-01-31 17:39:40 -06:00
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vpr ./test_vpr_arch/k6_frac_N10_40nm.xml ./test_blif/s298.blif --write_rr_graph example_rr_graph.xml
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2020-01-30 22:39:44 -06:00
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# Read OpenFPGA architecture definition
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read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
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# Annotate the OpenFPGA architecture to VPR data base
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link_openfpga_arch
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# Check and correct any naming conflicts in the BLIF netlist
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check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
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2020-02-05 22:50:52 -06:00
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# Apply fix-up to clustering nets based on routing results
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pb_pin_fixup --verbose
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2020-01-30 22:39:44 -06:00
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# Finish and exit OpenFPGA
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exit
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