204 lines
6.3 KiB
C++
204 lines
6.3 KiB
C++
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* Copyright (C) 2018-19 David Shah <david@symbioticeda.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct Ecp5FfinitPass : public Pass {
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Ecp5FfinitPass() : Pass("ecp5_ffinit", "ECP5: handle FF init values") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" ecp5_ffinit [options] [selection]\n");
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log("\n");
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log("Remove init values for FF output signals when equal to reset value.\n");
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log("If reset is not used, set the reset value to the init value, otherwise\n");
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log("unmap out the reset (if not an async reset).\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing ECP5_FFINIT pass (implement FF init values).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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// if (args[argidx] == "-singleton") {
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// singleton_mode = true;
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// continue;
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// }
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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log("Handling FF init values in %s.\n", log_id(module));
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SigMap sigmap(module);
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pool<Wire*> init_wires;
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dict<SigBit, State> initbits;
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dict<SigBit, SigBit> initbit_to_wire;
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pool<SigBit> handled_initbits;
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for (auto wire : module->selected_wires())
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{
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if (wire->attributes.count("\\init") == 0)
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continue;
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SigSpec wirebits = sigmap(wire);
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Const initval = wire->attributes.at("\\init");
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init_wires.insert(wire);
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for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++)
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{
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SigBit bit = wirebits[i];
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State val = initval[i];
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if (val != State::S0 && val != State::S1)
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continue;
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if (initbits.count(bit)) {
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if (initbits.at(bit) != val) {
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log_warning("Conflicting init values for signal %s (%s = %s, %s = %s).\n",
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log_signal(bit), log_signal(SigBit(wire, i)), log_signal(val),
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log_signal(initbit_to_wire[bit]), log_signal(initbits.at(bit)));
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initbits.at(bit) = State::Sx;
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}
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continue;
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}
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initbits[bit] = val;
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initbit_to_wire[bit] = SigBit(wire, i);
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}
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}
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for (auto cell : module->selected_cells())
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{
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if (cell->type != "\\TRELLIS_FF")
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continue;
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SigSpec sig_d = cell->getPort("\\DI");
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SigSpec sig_q = cell->getPort("\\Q");
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SigSpec sig_lsr = cell->getPort("\\LSR");
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if (GetSize(sig_d) < 1 || GetSize(sig_q) < 1)
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continue;
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SigBit bit_d = sigmap(sig_d[0]);
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SigBit bit_q = sigmap(sig_q[0]);
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std::string regset = "RESET";
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if (cell->hasParam("\\REGSET"))
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regset = cell->getParam("\\REGSET").decode_string();
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State resetState;
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if (regset == "SET")
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resetState = State::S1;
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else if (regset == "RESET")
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resetState = State::S0;
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else
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log_error("FF cell %s has illegal REGSET value %s.\n",
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log_id(cell), regset.c_str());
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if (!initbits.count(bit_q))
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continue;
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State val = initbits.at(bit_q);
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if (val == State::Sx)
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continue;
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log("FF init value for cell %s (%s): %s = %c\n", log_id(cell), log_id(cell->type),
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log_signal(bit_q), val != State::S0 ? '1' : '0');
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// Initval is the same as the reset state. Matches hardware, nowt more to do
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if (val == resetState) {
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handled_initbits.insert(bit_q);
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continue;
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}
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if (GetSize(sig_lsr) >= 1 && sig_lsr[0] != State::S0) {
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std::string srmode = "LSR_OVER_CE";
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if (cell->hasParam("\\SRMODE"))
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srmode = cell->getParam("\\SRMODE").decode_string();
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if (srmode == "ASYNC") {
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log("Async reset value %c for FF cell %s inconsistent with init value %c.\n",
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resetState != State::S0 ? '1' : '0', log_id(cell), val != State::S0 ? '1' : '0');
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} else {
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SigBit bit_lsr = sigmap(sig_lsr[0]);
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Wire *new_bit_d = module->addWire(NEW_ID);
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if (resetState == State::S0) {
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module->addAndnotGate(NEW_ID, bit_d, bit_lsr, new_bit_d);
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} else {
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module->addOrGate(NEW_ID, bit_d, bit_lsr, new_bit_d);
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}
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cell->setPort("\\DI", new_bit_d);
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cell->setPort("\\LSR", State::S0);
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if(cell->hasPort("\\CE")) {
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std::string cemux = "CE";
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if (cell->hasParam("\\CEMUX"))
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cemux = cell->getParam("\\CEMUX").decode_string();
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SigSpec sig_ce = cell->getPort("\\CE");
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if (GetSize(sig_ce) >= 1) {
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SigBit bit_ce = sigmap(sig_ce[0]);
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Wire *new_bit_ce = module->addWire(NEW_ID);
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if (cemux == "INV")
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module->addAndnotGate(NEW_ID, bit_ce, bit_lsr, new_bit_ce);
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else
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module->addOrGate(NEW_ID, bit_ce, bit_lsr, new_bit_ce);
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cell->setPort("\\CE", new_bit_ce);
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}
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}
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cell->setParam("\\REGSET", val != State::S0 ? Const("SET") : Const("RESET"));
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handled_initbits.insert(bit_q);
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}
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} else {
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cell->setParam("\\REGSET", val != State::S0 ? Const("SET") : Const("RESET"));
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handled_initbits.insert(bit_q);
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}
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}
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for (auto wire : init_wires)
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{
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if (wire->attributes.count("\\init") == 0)
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continue;
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SigSpec wirebits = sigmap(wire);
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Const &initval = wire->attributes.at("\\init");
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bool remove_attribute = true;
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for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++) {
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if (handled_initbits.count(wirebits[i]))
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initval[i] = State::Sx;
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else if (initval[i] != State::Sx)
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remove_attribute = false;
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}
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if (remove_attribute)
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wire->attributes.erase("\\init");
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}
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}
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}
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} Ecp5FfinitPass;
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PRIVATE_NAMESPACE_END
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