235 lines
12 KiB
C++
235 lines
12 KiB
C++
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/********************************************************************
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* This file include top-level function of FPGA-Verilog
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********************************************************************/
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/* Standard header files */
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#include <ctime>
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/* External library header files */
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#include "util.h"
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#include "vtr_assert.h"
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#include "circuit_library_utils.h"
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/* FPGA-X2P header files */
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#include "fpga_x2p_utils.h"
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#include "rr_blocks.h"
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/* FPGA-Verilog header files */
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#include "verilog_global.h"
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#include "verilog_submodules.h"
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#include "verilog_routing.h"
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#include "verilog_submodules.h"
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#include "verilog_grid.h"
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#include "verilog_routing.h"
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#include "verilog_top_module.h"
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#include "verilog_top_testbench.h"
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#include "verilog_formal_random_top_testbench.h"
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#include "verilog_preconfig_top_module.h"
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#include "simulation_info_writer.h"
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#include "verilog_auxiliary_netlists.h"
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/* Header file for this source file */
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#include "verilog_api.h"
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/********************************************************************
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* Top-level function of FPGA-Verilog
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* This function will generate
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* 1. primitive modules required by the full fabric
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* which are LUTs, routing multiplexer, logic gates, transmission-gates etc.
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* 2. Routing modules, which are Switch Blocks (SBs) and Connection Blocks (CBs)
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* 3. Logic block modules, which are Configuration Logic Blocks (CLBs)
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* 4. FPGA module, which are the full FPGA fabric with configuration protocol
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* 5. A wrapper module, which encapsulate the FPGA module in a Verilog module which have the same port as the input benchmark
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* 6. Testbench, where a FPGA module is configured with a bitstream and then driven by input vectors
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* 7. Pre-configured testbench, which can skip the configuration phase and pre-configure the FPGA module. This testbench is created for quick verification and formal verification purpose.
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* 8. Verilog netlist including preprocessing flags and all the Verilog netlists that have been generated
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********************************************************************/
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void vpr_fpga_verilog(ModuleManager& module_manager,
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const BitstreamManager& bitstream_manager,
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const std::vector<ConfigBitId>& fabric_bitstream,
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const MuxLibrary& mux_lib,
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const std::vector<t_logical_block>& L_logical_blocks,
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const vtr::Point<size_t>& device_size,
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const std::vector<std::vector<t_grid_tile>>& L_grids,
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const std::vector<t_block>& L_blocks,
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const DeviceRRGSB& L_device_rr_gsb,
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const t_vpr_setup& vpr_setup,
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const t_arch& Arch,
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const std::string& circuit_name,
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t_sram_orgz_info* sram_verilog_orgz_info) {
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/* Start time count */
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clock_t t_start = clock();
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/* 0. basic units: inverter, buffers and pass-gate logics, */
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/* Check if the routing architecture we support*/
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if (UNI_DIRECTIONAL != vpr_setup.RoutingArch.directionality) {
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vpr_printf(TIO_MESSAGE_ERROR,
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"FPGA-Verilog only supports uni-directional routing architecture!\n");
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exit(1);
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}
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/* We don't support mrFPGA */
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#ifdef MRFPGA_H
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if (is_mrFPGA) {
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vpr_printf(TIO_MESSAGE_ERROR,
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"FPGA-Verilog does not support mrFPGA!\n");
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exit(1);
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}
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#endif
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/* Verilog generator formally starts*/
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vpr_printf(TIO_MESSAGE_INFO,
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"\nFPGA-Verilog starts...\n");
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/* Format the directory paths */
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std::string chomped_parent_dir = find_path_dir_name(circuit_name);
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std::string chomped_circuit_name = find_path_file_name(circuit_name);
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std::string verilog_dir_formatted;
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if (NULL != vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.syn_verilog_dump_dir) {
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verilog_dir_formatted = format_dir_path(std::string(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.syn_verilog_dump_dir));
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} else {
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verilog_dir_formatted = format_dir_path(format_dir_path(chomped_parent_dir) + std::string(default_verilog_dir_name));
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}
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/* Create directories */
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create_dir_path(verilog_dir_formatted.c_str());
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/* SRC directory to contain all the netlists */
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std::string src_dir_path = format_dir_path(verilog_dir_formatted + std::string(default_src_dir_name));
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create_dir_path(src_dir_path.c_str());
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/* Sub directory under SRC directory to contain all the primitive block netlists */
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std::string submodule_dir_path = src_dir_path + std::string(default_submodule_dir_name);
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create_dir_path(submodule_dir_path.c_str());
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/* Sub directory under SRC directory to contain all the logic block netlists */
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std::string lb_dir_path = src_dir_path + std::string(default_lb_dir_name);
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create_dir_path(lb_dir_path.c_str());
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/* Sub directory under SRC directory to contain all the routing block netlists */
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std::string rr_dir_path = src_dir_path + std::string(default_rr_dir_name);
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create_dir_path(rr_dir_path.c_str());
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/* Ensure all the SRAM port is using the correct circuit model */
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config_circuit_models_sram_port_to_default_sram_model(Arch.spice->circuit_lib, Arch.sram_inf.verilog_sram_inf_orgz->circuit_model);
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/* Print Verilog files containing preprocessing flags */
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print_verilog_preprocessing_flags_netlist(std::string(src_dir_path),
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vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts);
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print_verilog_simulation_preprocessing_flags(std::string(src_dir_path),
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vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts);
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/* Generate primitive Verilog modules, which are corner stones of FPGA fabric
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* Note that this function MUST be called before Verilog generation of
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* core logic (i.e., logic blocks and routing resources) !!!
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* This is because that this function will add the primitive Verilog modules to
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* the module manager.
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* Without the modules in the module manager, core logic generation is not possible!!!
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*/
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print_verilog_submodules(module_manager, mux_lib, sram_verilog_orgz_info, src_dir_path.c_str(), submodule_dir_path.c_str(),
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Arch, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts);
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/* Generate routing blocks */
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if (TRUE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy) {
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print_verilog_unique_routing_modules(module_manager, L_device_rr_gsb,
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vpr_setup.RoutingArch,
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src_dir_path, rr_dir_path,
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TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog);
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} else {
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VTR_ASSERT(FALSE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy);
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print_verilog_flatten_routing_modules(module_manager, L_device_rr_gsb,
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vpr_setup.RoutingArch,
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src_dir_path, rr_dir_path,
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TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog);
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}
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/* Generate grids */
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print_verilog_grids(module_manager,
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src_dir_path, lb_dir_path,
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TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog);
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/* Generate FPGA fabric */
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print_verilog_top_module(module_manager,
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std::string(vpr_setup.FileNameOpts.ArchFile),
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src_dir_path,
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TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog);
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/* Collect global ports from the circuit library
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* TODO: move outside this function
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*/
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std::vector<CircuitPortId> global_ports = find_circuit_library_global_ports(Arch.spice->circuit_lib);
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/* Generate wrapper module for FPGA fabric (mapped by the input benchmark and pre-configured testbench for verification */
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if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_formal_verification_top_netlist) {
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std::string formal_verification_top_netlist_file_path = src_dir_path + chomped_circuit_name
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+ std::string(formal_verification_verilog_file_postfix);
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print_verilog_preconfig_top_module(module_manager, bitstream_manager,
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Arch.spice->circuit_lib, global_ports, L_logical_blocks,
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device_size, L_grids, L_blocks,
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std::string(chomped_circuit_name), formal_verification_top_netlist_file_path,
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std::string(src_dir_path));
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/* Generate top-level testbench using random vectors */
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std::string random_top_testbench_file_path = src_dir_path + chomped_circuit_name
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+ std::string(random_top_testbench_verilog_file_postfix);
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print_verilog_random_top_testbench(chomped_circuit_name, random_top_testbench_file_path,
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src_dir_path, L_logical_blocks,
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vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, Arch.spice->spice_params);
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}
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/* Generate exchangeable files which contains simulation settings */
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if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_simulation_ini) {
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std::string simulation_ini_file_name;
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if (NULL != vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.simulation_ini_path) {
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simulation_ini_file_name = std::string(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.simulation_ini_path);
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}
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print_verilog_simulation_info(simulation_ini_file_name,
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format_dir_path(chomped_parent_dir),
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chomped_circuit_name,
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src_dir_path,
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bitstream_manager.bits().size(),
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Arch.spice->spice_params.meas_params.sim_num_clock_cycle,
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Arch.spice->spice_params.stimulate_params.prog_clock_freq,
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Arch.spice->spice_params.stimulate_params.op_clock_freq);
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}
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/* Generate full testbench for verification, including configuration phase and operating phase */
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if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_autocheck_top_testbench) {
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std::string autocheck_top_testbench_file_path = src_dir_path + chomped_circuit_name
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+ std::string(autocheck_top_testbench_verilog_file_postfix);
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print_verilog_top_testbench(module_manager, bitstream_manager, fabric_bitstream,
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sram_verilog_orgz_info->type,
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Arch.spice->circuit_lib, global_ports,
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L_logical_blocks, device_size, L_grids, L_blocks,
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chomped_circuit_name,
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autocheck_top_testbench_file_path,
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src_dir_path,
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Arch.spice->spice_params);
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}
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/* Generate a Verilog file including all the netlists that have been generated */
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std::string ref_verilog_benchmark_file_name;
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if (NULL != vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.reference_verilog_benchmark_file) {
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ref_verilog_benchmark_file_name = std::string(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.reference_verilog_benchmark_file);
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}
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print_include_netlists(src_dir_path,
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chomped_circuit_name,
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ref_verilog_benchmark_file_name,
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Arch.spice->circuit_lib);
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/* Given a brief stats on how many Verilog modules have been written to files */
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vpr_printf(TIO_MESSAGE_INFO,
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"Outputted %lu Verilog modules in total\n",
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module_manager.num_modules());
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/* End time count */
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clock_t t_end = clock();
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float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC;
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vpr_printf(TIO_MESSAGE_INFO,
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"FPGA-Verilog took %g seconds\n",
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run_time_sec);
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}
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