200 lines
8.2 KiB
C++
200 lines
8.2 KiB
C++
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/********************************************************************
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* This file includes functions to print Verilog modules for a Grid
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* (CLBs, I/Os, heterogeneous blocks etc.)
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*******************************************************************/
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/* System header files */
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#include <vector>
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#include <fstream>
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/* Header files from external libs */
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#include "util.h"
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#include "vtr_assert.h"
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/* Header files for VPR */
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#include "vpr_types.h"
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#include "globals.h"
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/* Header files for FPGA X2P tool suite */
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#include "fpga_x2p_naming.h"
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#include "fpga_x2p_utils.h"
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/* Header files for Verilog generator */
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#include "verilog_global.h"
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#include "verilog_utils.h"
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#include "verilog_writer_utils.h"
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#include "verilog_grid.h"
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/*****************************************************************************
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* This function will create a Verilog file and print out a Verilog netlist
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* for a type of physical block
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*
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* For IO blocks:
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* The param 'border_side' is required, which is specify which side of fabric
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* the I/O block locates at.
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*****************************************************************************/
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static
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void print_verilog_grid(ModuleManager& module_manager,
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const MuxLibrary& mux_lib,
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const CircuitLibrary& circuit_lib,
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t_sram_orgz_info* cur_sram_orgz_info,
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const std::string& verilog_dir,
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const std::string& subckt_dir,
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t_type_ptr phy_block_type,
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const e_side& border_side,
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const bool& use_explicit_mapping) {
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/* Check code: if this is an IO block, the border side MUST be valid */
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if (IO_TYPE == phy_block_type) {
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VTR_ASSERT(NUM_SIDES != border_side);
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}
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/* Give a name to the Verilog netlist */
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/* Create the file name for Verilog */
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std::string verilog_fname(subckt_dir
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+ generate_physical_block_netlist_name(std::string(phy_block_type->name),
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IO_TYPE == phy_block_type,
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border_side,
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std::string(verilog_netlist_file_postfix))
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);
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/* TODO: remove the bak file when the file is ready */
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verilog_fname += ".bak";
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/* Echo status */
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if (IO_TYPE == phy_block_type) {
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Side side_manager(border_side);
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vpr_printf(TIO_MESSAGE_INFO,
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"Writing FPGA Verilog Netlist (%s) for logic block %s at %s side ...\n",
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verilog_fname.c_str(), phy_block_type->name,
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side_manager.c_str());
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} else {
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vpr_printf(TIO_MESSAGE_INFO,
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"Writing FPGA Verilog Netlist (%s) for logic block %s...\n",
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verilog_fname.c_str(), phy_block_type->name);
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}
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/* Create the file stream */
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std::fstream fp;
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fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
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check_file_handler(fp);
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print_verilog_file_header(fp, std::string("Verilog modules for physical block: " + std::string(phy_block_type->name) + "]"));
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/* Print preprocessing flags */
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print_verilog_include_defines_preproc_file(fp, verilog_dir);
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/* TODO: Print Verilog modules for all the pb_types/pb_graph_nodes */
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for (int iz = 0; iz < phy_block_type->capacity; ++iz) {
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/* ONLY output one Verilog module (which is unique), others are the same */
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if (0 < iz) {
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continue;
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}
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/* TODO: use a Depth-First Search Algorithm to print the sub-modules
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* Note: DFS is the right way. Do NOT use BFS.
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* DFS can guarantee that all the sub-modules can be registered properly
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* to its parent in module manager
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*/
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print_verilog_comment(fp, std::string("---- BEGIN Sub-module of physical block:" + std::string(phy_block_type->name) + " ----"));
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/* Print Verilog modules starting from the top-level pb_type/pb_graph_node, and traverse the graph in a recursive way */
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/*
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dump_verilog_phy_pb_graph_node_rec(cur_sram_orgz_info, fp, subckt_name_prefix,
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phy_block_type->pb_graph_head, iz,
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is_explicit_mapping);
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*/
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print_verilog_comment(fp, std::string("---- END Sub-module of physical block:" + std::string(phy_block_type->name) + " ----"));
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}
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/* TODO: Create a Verilog Module for the top-level physical block, and add to module manager */
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std::string module_name = generate_physical_block_module_name(std::string(grid_verilog_file_name_prefix), phy_block_type->name, IO_TYPE == phy_block_type, border_side);
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ModuleId module_id = module_manager.add_module(module_name);
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/* TODO: Add ports to the module */
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/* TODO: Print the module definition for the top-level Verilog module of physical block */
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print_verilog_module_declaration(fp, module_manager, module_id);
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/* Finish printing ports */
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/* Print an empty line a splitter */
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fp << std::endl;
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/* TODO: instanciate all the sub modules */
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for (int iz = 0; iz < phy_block_type->capacity; ++iz) {
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}
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/* Put an end to the top-level Verilog module of physical block */
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print_verilog_module_end(fp, module_manager.module_name(module_id));
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/* Add an empty line as a splitter */
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fp << std::endl;
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/* Close file handler */
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fp.close();
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/* Add fname to the linked list */
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/*
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grid_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(grid_verilog_subckt_file_path_head, verilog_fname.c_str());
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*/
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}
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/*****************************************************************************
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* Create logic block modules in a compact way:
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* 1. Only one module for each I/O on each border side (IO_TYPE)
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* 2. Only one module for each CLB (FILL_TYPE)
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* 3. Only one module for each heterogeneous block
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****************************************************************************/
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void print_verilog_grids(ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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const MuxLibrary& mux_lib,
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t_sram_orgz_info* cur_sram_orgz_info,
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const std::string& verilog_dir,
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const std::string& subckt_dir,
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const bool& is_explicit_mapping) {
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/* Enumerate the types, dump one Verilog module for each */
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for (int itype = 0; itype < num_types; itype++) {
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if (EMPTY_TYPE == &type_descriptors[itype]) {
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/* Bypass empty type or NULL */
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continue;
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} else if (IO_TYPE == &type_descriptors[itype]) {
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/* Special for I/O block, generate one module for each border side */
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for (int iside = 0; iside < NUM_SIDES; iside++) {
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Side side_manager(iside);
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print_verilog_grid(module_manager, mux_lib, circuit_lib,
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cur_sram_orgz_info,
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verilog_dir, subckt_dir,
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&type_descriptors[itype],
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side_manager.get_side(),
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is_explicit_mapping);
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}
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continue;
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} else if (FILL_TYPE == &type_descriptors[itype]) {
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/* For CLB */
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print_verilog_grid(module_manager, mux_lib, circuit_lib,
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cur_sram_orgz_info,
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verilog_dir, subckt_dir,
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&type_descriptors[itype],
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NUM_SIDES,
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is_explicit_mapping);
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continue;
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} else {
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/* For heterogenenous blocks */
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print_verilog_grid(module_manager, mux_lib, circuit_lib,
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cur_sram_orgz_info,
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verilog_dir, subckt_dir,
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&type_descriptors[itype],
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NUM_SIDES,
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is_explicit_mapping);
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}
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}
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/* Output a header file for all the logic blocks */
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vpr_printf(TIO_MESSAGE_INFO, "Generating header file for grid Verilog modules...\n");
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std::string grid_verilog_fname(logic_block_verilog_file_name);
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/* TODO: remove .bak when it is ready */
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grid_verilog_fname += ".bak";
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dump_verilog_subckt_header_file(grid_verilog_subckt_file_path_head,
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subckt_dir.c_str(),
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grid_verilog_fname.c_str());
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}
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