OpenFPGA/yosys/tests/simple/implicit_ports.v

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2019-11-27 15:40:39 -06:00
// Test implicit port connections
module alu (input [2:0] a, input [2:0] b, input cin, output cout, output [2:0] result);
assign cout = cin;
assign result = a + b;
endmodule
module named_ports(input [2:0] a, b, output [2:0] alu_result, output cout);
wire cin = 1;
alu alu (
.a(a),
.b, // Implicit connection is equivalent to .b(b)
.cin(), // Explicitely unconnected
.cout(cout),
.result(alu_result)
);
endmodule