35 lines
2.5 KiB
Plaintext
35 lines
2.5 KiB
Plaintext
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# Standard Configuration Example
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[dir_path]
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#benchmark_dir = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/vtr_benchmarks_verilog
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#benchmark_dir = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/vtr_benchmarks_blif
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#benchmark_dir = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/MCNC_big20
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benchmark_dir = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/fpga_spice_test_bench
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odin2_path = /home/xitang/research/vtr_release/ODIN_II/odin_II.exe
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cirkit_path = /home/xitang/tangxifan-eda-tools/branches/FPGA_MIG/abc_majccmap/abc
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abc_path = /home/xitang/research/ABC/abc70930/abc
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abc_mccl_path = /home/xitang/tangxifan-eda-tools/branches/FPGA_MIG/abc_vtrccmap/abc
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abc_with_bb_support_path = /home/xitang/research/vtr_release/abc_with_bb_support/abc
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mpack1_path = /home/xitang/tangxifan-eda-tools/branches/MPACK_v1.5b/mpack
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m2net_path = /home/xitang/tangxifan-eda-tools/branches/scripts/m2net.pl
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mpack2_path = /home/xitang/tangxifan-eda-tools/branches/MPACK_v2/mpack2
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#vpr_path = /home/xitang/research/vtr_release/vpr/vpr
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vpr_path = /home/xitang/tangxifan-eda-tools/branches/vpr7_rram/vpr/vpr
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rpt_dir = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/results
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ace_path = /home/xitang/research/vtr_release/ace2/ace
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[flow_conf]
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flow_type = standard #standard|mpack2|mpack1|vtr_standard|vtr
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#flow_type = vtr #standard|mpack2|mpack1|vtr_standard|vtr
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vpr_arch = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm.xml # Use relative path under VPR folder is OK
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mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK
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m2net_conf = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/m2net_conf/m2x2_SiNWFET.conf
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mpack2_arch = K6_pattern7_I24.arch
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#power_tech_xml = /home/xitang/research/vtr_release/vtr_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK
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power_tech_xml = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/power_tech_properties/tsmc40nm.xml # Use relative path under VPR folder is OK
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[csv_tags]
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mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf:
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mpack2_tags = BLE Number:|BLE Fill Rate:
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vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took|Average net density:|Median net density:|Recommend no. of clock cycles:
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vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc Structures|lut6|ff
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