2020-02-20 21:26:20 -06:00
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/***************************************************************************************
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* This file includes functions that are used to redo packing for physical pbs
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***************************************************************************************/
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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#include "lb_router_utils.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/***************************************************************************************
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* Add a net to route to a logical block router
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* This function will automatically find the source and sink atom pins
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* based on the given atom net
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***************************************************************************************/
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LbRouter::NetId add_lb_router_net_to_route(LbRouter& lb_router,
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2020-02-20 22:56:15 -06:00
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const LbRRGraph& lb_rr_graph,
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2020-02-20 21:26:20 -06:00
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const LbRRNodeId& source_node,
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const std::vector<LbRRNodeId>& sink_nodes,
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2020-02-20 22:56:15 -06:00
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const AtomContext& atom_ctx,
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2020-02-20 21:26:20 -06:00
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const AtomNetId& atom_net_id) {
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VTR_ASSERT(0 < sink_nodes.size());
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LbRouter::NetId lb_net = lb_router.create_net_to_route(source_node, sink_nodes);
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VTR_ASSERT(AtomNetId::INVALID() != atom_net_id);
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lb_router.add_net_atom_net_id(lb_net, atom_net_id);
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2020-02-20 22:56:15 -06:00
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2020-02-20 21:26:20 -06:00
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std::vector<AtomPinId> terminal_pins;
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2020-02-20 22:56:15 -06:00
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AtomPinId atom_pin_outside_pb = AtomPinId::INVALID();
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for (const LbRRNodeId& sink_node : sink_nodes) {
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t_pb_graph_pin* sink_pb_pin = lb_rr_graph.node_pb_graph_pin(sink_node);
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bool atom_pin_inside_pb = false;
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for (const AtomPinId& atom_pin : atom_ctx.nlist.net_sinks(atom_net_id)) {
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VTR_ASSERT(AtomPinId::INVALID() != atom_pin);
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if (sink_pb_pin == find_pb_graph_pin(atom_ctx.nlist, atom_ctx.lookup, atom_pin)) {
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terminal_pins.push_back(atom_pin);
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atom_pin_inside_pb = true;
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break;
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}
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if (AtomPinId::INVALID() == atom_pin_outside_pb) {
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atom_pin_outside_pb = atom_pin;
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}
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}
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/* Add a atom pin which is not inside the pb */
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if (false == atom_pin_inside_pb) {
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VTR_ASSERT(AtomPinId::INVALID() != atom_pin_outside_pb);
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terminal_pins.push_back(atom_pin_outside_pb);
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}
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2020-02-20 21:26:20 -06:00
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}
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2020-02-20 22:56:15 -06:00
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VTR_ASSERT(AtomPinId::INVALID() != atom_ctx.nlist.net_driver(atom_net_id));
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if (sink_nodes.size() != terminal_pins.size()) {
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VTR_LOGF_ERROR(__FILE__, __LINE__,
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"Net '%s' has %lu sink nodes while has %lu associated atom pins!\n",
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atom_ctx.nlist.net_name(atom_net_id).c_str(),
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sink_nodes.size(),
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terminal_pins.size());
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}
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VTR_ASSERT(sink_nodes.size() == terminal_pins.size());
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lb_router.add_net_atom_pins(lb_net, atom_ctx.nlist.net_driver(atom_net_id), terminal_pins);
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2020-02-20 21:26:20 -06:00
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return lb_net;
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}
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} /* end namespace openfpga */
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