38 lines
803 B
Tcl
38 lines
803 B
Tcl
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echo "=========================="
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pwd
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echo "=========================="
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set projectname ${PROJECTNAME}
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set benchmark ${BENCHMARK}
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set top_tb ${TOP_TB}
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#in ms
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set simtime ${SIMTIME}
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set unit ${UNIT}
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#Path were both tcl script are located
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set verilog_path ${VERILOG_PATH}
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set project_path "${MODELSIM_PROJ_DIR}/msim_projects/"
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#Path were the verilog files are located
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set verilog_path ${VERILOG_PATH}
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set verilog_files [list \
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${VERILOG_PATH}${VERILOG_FILE1} \
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${VERILOG_PATH}${VERILOG_FILE2} \
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${VERILOG_PATH}fpga_defines.v
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]
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#Source the tcl script
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source ${MODELSIM_PROJ_DIR}/${BENCHMARK}_autocheck_proc.tcl
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#Execute the top level procedure
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try {
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top_create_new_project $$projectname $$verilog_files $$project_path $$simtime $$unit $$top_tb
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} finally {
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quit
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}
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#Relaunch simulation
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