43 lines
1.4 KiB
Bash
43 lines
1.4 KiB
Bash
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python3.5 openfpga_flow/scripts/run_fpga_flow.py \
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./openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml \
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./openfpga_flow/benchmarks/MCNC_Verilog/s298/s298.v \
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--top_module s298 \
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--power \
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--power_tech ./openfpga_flow/tech/winbond90nm/winbond90nm_power_properties.xml \
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--min_route_chan_width 1.3 \
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--vpr_fpga_verilog \
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--vpr_fpga_verilog_dir ./SRC \
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--vpr_fpga_x2p_rename_illegal_port \
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--vpr_fpga_verilog_print_autocheck_top_testbench
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# \
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# --end_flow_with_test \
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# --vpr_fpga_verilog_print_autocheck_top_testbench \
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# --vpr_fpga_verilog_include_icarus_simulator \
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# --vpr_fpga_verilog_formal_verification_top_netlist
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# '/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/vpr',
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# '/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/tmp/arch/k6_N10_rram_memory_bank_SC_winbond90.xml', 's298_ace_corrected_out.blif'
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# '--net_file'
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# 's298_vpr.net'
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# '--place_file'
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# 's298_vpr.place'
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# '--route_file'
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# 's298_vpr.route'
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# '--full_stats'
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# '--nodisp'
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# '--power'
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# '--activity_file'
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# 's298_ace_out.act'
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# '--tech_properties'
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# '/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/openfpga_flow/tech/winbond90nm/winbond90nm_power_properties.xml'
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# '--fpga_verilog'
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# '--fpga_verilog_dir'
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# './SRC'
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# '--fpga_verilog_print_autocheck_top_testbench'
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# 's298_output_verilog.v'
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# '--fpga_verilog_print_formal_verification_top_netlist'
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# '--fpga_verilog_include_icarus_simulator'
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# '--fpga_x2p_rename_illegal_port'
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