9 lines
382 B
XML
9 lines
382 B
XML
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<ports>
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<port core_name="prog_clock[0]" top_name="prog_clk0"/>
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<port core_name="prog_clock[1]" top_name="prog_clk1"/>
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<port core_name="gfpga_io_pad[0:31]" top_name="top_io[0:31]"/>
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<port core_name="gfpga_io_pad[32:47]" top_name="right_io[32:47]"/>
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<port core_name="gfpga_io_pad[48:55]" top_name="bottom_io[48:55]"/>
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<port top_name="pvt_sense" is_dummy="true"/>
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</ports>
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