108 lines
4.1 KiB
C
108 lines
4.1 KiB
C
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/******************************************************************************
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* This files includes data structures for netlist management.
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* It keeps a list of netlists that have been created
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* Each netlist includes a list of ids of modules that are stored in ModuleManager
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*
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* When we want to dump out a netlist in Verilog/SPICE format,
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* the netlist manager can generate the dependency on other netlists
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* This can help us tracking the dependency and generate `include` files easily
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*
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* Cross-reference:
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*
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* +---------+ +---------+
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* | | ModuleId | |
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* | Netlist |-------------->| Module |
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* | Manager | | Manager |
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* | | | |
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* +---------+ +---------+
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*
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******************************************************************************/
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#ifndef NETLIST_MANAGER_H
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#define NETLIST_MANAGER_H
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#include <string>
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#include <vector>
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#include <map>
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#include "vtr_vector.h"
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#include "netlist_manager_fwd.h"
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#include "module_manager.h"
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/* begin namespace openfpga */
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namespace openfpga {
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class NetlistManager {
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public: /* Internal Types */
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/* Type of netlists */
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enum e_netlist_type {
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SUBMODULE_NETLIST,
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LOGIC_BLOCK_NETLIST,
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ROUTING_MODULE_NETLIST,
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TOP_MODULE_NETLIST,
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TESTBENCH_NETLIST,
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NUM_NETLIST_TYPES
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};
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public: /* Types and ranges */
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typedef vtr::vector<NetlistId, NetlistId>::const_iterator netlist_iterator;
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typedef vtr::Range<netlist_iterator> netlist_range;
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public: /* Public aggregators */
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/* Find all the netlists */
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netlist_range netlists() const;
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/* Find all the modules that are included in a netlist */
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std::vector<ModuleId> netlist_modules(const NetlistId& netlist) const;
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/* Find all the preprocessing flags that are included in a netlist */
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std::vector<std::string> netlist_preprocessing_flags(const NetlistId& netlist) const;
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public: /* Public accessors */
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/* Find the name of a netlist */
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std::string netlist_name(const NetlistId& netlist) const;
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/* Find a netlist by its name */
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NetlistId find_netlist(const std::string& netlist_name) const;
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/* Get the type of a netlist */
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e_netlist_type netlist_type(const NetlistId& netlist) const;
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/* Find if a module belongs to a netlist */
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bool is_module_in_netlist(const NetlistId& netlist, const ModuleId& module) const;
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/* Find the netlist that a module belongs to */
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NetlistId find_module_netlist(const ModuleId& module) const;
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public: /* Public mutators */
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/* Add a netlist to the library */
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NetlistId add_netlist(const std::string& name);
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/* Set a netlist type */
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void set_netlist_type(const NetlistId& netlist,
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const e_netlist_type& type);
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/* Add a module to a netlist in the library */
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bool add_netlist_module(const NetlistId& netlist, const ModuleId& module);
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/* Add a pre-processing flag to a netlist */
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void add_netlist_preprocessing_flag(const NetlistId& netlist, const std::string& preprocessing_flag);
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public: /* Public validators/invalidators */
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bool valid_netlist_id(const NetlistId& netlist) const;
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private: /* Private validators/invalidators */
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bool valid_preprocessing_flag_id(const PreprocessingFlagId& flag) const;
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void invalidate_name2id_map();
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void invalidate_module2netlist_map();
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private: /* Internal data */
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vtr::vector<NetlistId, NetlistId> netlist_ids_;
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vtr::vector<NetlistId, std::string> netlist_names_;
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vtr::vector<NetlistId, e_netlist_type> netlist_types_;
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vtr::vector<NetlistId, std::vector<ModuleId>> included_module_ids_;
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vtr::vector<NetlistId, std::vector<PreprocessingFlagId>> included_preprocessing_flag_ids_;
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vtr::vector<PreprocessingFlagId, PreprocessingFlagId> preprocessing_flag_ids_;
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vtr::vector<PreprocessingFlagId, std::string> preprocessing_flag_names_;
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/* fast look-up for netlist */
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std::map<std::string, NetlistId> name_id_map_;
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/* fast look-up for modules in netlists */
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std::map<ModuleId, NetlistId> module_netlist_map_;
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};
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} /* end namespace openfpga */
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#endif
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